Method and apparatus for testing batteries

• US 4,827,220 A
• Filed: 10/26/1987
• Issued: 05/02/1989
• Est. Priority Date: 10/26/1987
• Status: Expired due to Fees

• Current Assignee: PNC Bank National Association (The PNC Financial Services Group, Inc.)
• Original Assignee: Intermark Corp. (Mergence Corp.)
• Inventors: Figh, Jack N.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/113,632
• Time in Patent Office: 554 Days
• Field of Search: 324/426, 324/428, 324/429, 324/430, 324/433, 320/48, 340/636
• US Class Current: 324/426
• CPC Class Codes: G01R 19/16542 for batteries charge condition monitoring in G01R31/36

Abstract

A circuit for testing a computer battery without removing it from the computer includes a plurality of serially connected resistors, and a transistor connected to saturate. The voltages at the junctions of the transistors is sensed by a logic device such as a buffer, for application to the data bus of the computer. The transistor may be controlled from the computer via a latch. The resistors have values to produce voltages at two sensed resistor junctions such that the corresponding logic levels applied to the computer are the same, at a first level, when the battery voltage is acceptable, are the same at another logic level when the battery voltage is unacceptable, and are different when the battery voltage is between acceptable and unacceptable voltage values.

Claims

1. A circuit for testing the condition of a battery and having a pair of terminals to which a battery is adapted to be connected, said circuit comprising a series circuit of a plurality of resistors and a switching means, said resistors defining first and second junctions, control means for controlling said switching means to connect said resistors between said terminals, and sensing means for sensing the voltage levels at said first and second junctions of said resistors, said sensing means comprising threshold sensing means for producing first and second logic level outputs in response to determined voltages at said first and second junctions, and means for enabling said sensing means to sense the voltages at said first and second junctions, whereby the condition of a battery connected to said terminals is indicated by the voltages sensed at both said first and second junctions at any given time.

2. The circuit of claim 1 wherein said switching means comprises a transistor and said control means for said switching means comprises a latching circuit, and means for controlling said latching circuit to apply a saturation bias to said transistor.

3. The circuit of claim 1 wherein said sensing means comprises a logic element having first and second inputs and first and second outputs, the voltage at said outputs being of either a logic HIGH level or a logic LOW level, said logic element being selectively responsive to voltages above a minimum first voltage and below a maximum second voltage, for establishing the output level thereof, said second voltage being less than said first voltage.

4. The circuit of claim 3 wherein said plurality of resistors comprises first, second and third resistors, said resistors having values to set both of the logic element outputs to a first level when the battery has an acceptable voltage, to set both of the logic element outputs to a second level when the battery has an unacceptable voltage, and to set the logic element outputs to different levels when the voltage of said battery is between said first and second voltages.

5. The circuit of claim 4 wherein said logic element comprises a buffer, and said means enabling said sensing means comprises means for enabling said buffer.

6. The circuit of claim 5 wherein said buffer is a TTL buffer.

7. The circuit of claim 5 wherein said switching means comprises a transistor and said control means for said switching means comprises a latching circuit, and means for controlling said latching circuit to apply a saturation bias to said transistor.

8. The circuit of claim 7 wherein said means controlling said latching circuit comprises a computer having an addressable output connected to said latching circuit as a clock signal, said computer being connected to receive the output of said buffer.

9. The circuit of claim 8 wherein said computer comprises loudspeaker means, and means responsive to the outputs of said buffer for controlling the tone of audio signals emitted by said loudspeaker means.

12. The circuit of claim 1 further comprising operating supply terminal means independent of said pair of terminals adapted to be connected to a source of operating voltage, wherein said sensing means comprises a buffer having first and second inputs, each of said inputs being connected to a separate one of said junctions by way of a second diode, each of said inputs being connected to said supply terminal by way of a separate resistor.

13. The circuit of claim 12 wherein said buffer has first and second outputs and said enabling means comprises an enable terminal on said buffer for enabling the application of determined logic level voltages at said first and second outputs in response to the application of determined logic level voltages at said first and second inputs, respectively.

14. The circuit of claim 1 wherein said first junction is at a higher voltage position of said series resistors than said second junction, and further comprising means responsive to the output voltages of said sensing means when the voltages at said first and second junctions are above a first level for indicating that a battery connected to said terminals is good, means responsive to the output voltages of said sensing means when the voltage at said first junction is above said first level and the voltage at said second junction below a second level for indicating that the battery is marginal, and means responsive to the output voltages of said sensing means when the voltage at said first and second junctions is below said second level for indicating that said battery should be replaced.

15. The circuit of claim 14 wherein said sensing means comprises a buffer, and first and second comparing means connecting said buffer to said first and second junctions, respectively.

16. The circuit of claim 15 wherein said comparing means comprises diodes connecting said buffer to said junctions, a terminal adapted to be connected to a source of a reference potential, and resistors connecting said buffer to said terminal.

10. The method of determining the condition of a battery comprising controlling a transistor to pass saturation current from the battery through first, second and third serially connected resistors, sensing the voltage at a first junction between said first and second resistors with a first threshold device to establish the output level of the first threshold device at a first level when the voltage at said first junction is above a first voltage, and simultaneously sensing the voltage at a second junction between said second and third resistor with a second threshold device to establish the output level of the second threshold device at a second level when the voltage at said second junction is below a second voltage, said second voltage being less than said first voltage.

11. The method of claim 10 comprising adjusting the relative values of said resistors to produce the same first level outputs of said threshold devices when the battery voltage is acceptable, to produce the same second level outputs of said threshold devices when the battery voltage is unacceptable, and to produce different level outputs when the voltage of said battery is between acceptable and unacceptable voltages.