Instantaneous incremental compiler for producing logic circuit designs

• US 4,827,427 A
• Filed: 03/05/1987
• Issued: 05/02/1989
• Est. Priority Date: 03/05/1987
• Status: Expired due to Term

• Current Assignee: Stanley M. Hyduke
• Original Assignee: Stanley M. Hyduke
• Inventors: Hyduke, Stanley M.
• Primary Examiner(s): Gruber, Felix D.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/021,925
• Time in Patent Office: 789 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/300, 364/200
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A computer aided logic design system for instantaneously compiling circuit component entries into a schematic model which provides immediate simulation of each entry or deletion into the electronic circuit schematic. The system includes software for processing logic designs which produces a signal table for storing all inputs and outputs of chips stored in a specification table. The processor also produces a call table that lists all chips from the chips specification table from which chip models can be retreived and executed. Additionally, a software routine produces a netlist transfer table that specifies the transfer of signals within the signal table produced by software processing, which correspond to the signal distribution in the circuit being designed. After production of the signal table, specification table, call table and netlist transfer table, a software processing routine executes sequential values retrieved from the call table and netlist transfer table to create a second signal table which is compared with the first signal table. The software processing routine continuous to execute values retrieved from the call table and netlist transfer table and compare the first and second signal tables until both the second signal table being created is identical with the first signal table stored in memory. The software processing means also includes a delay which delays sequential processing until the comparing step for comparing the second signal table with the first signal table reaches a stable state.

Claims

1. A system for integrated circuit design and simulating operation comprising;

storage means for storing behavorial models of integrated circuit chips;

first circuit processing means for selecting one or more integrated circuit models from said storage means;

automatic drawing means for automatically drawing inputs and outputs of said selected integrated circuit models to produce integrated circuit design data;

simulating means for simulating inputs and outputs to and from said integrated circuit design;

second storage means storing tables of electronic component specifications;

said tables including;

a signal table storing all inputs and outputs of said integrated circuit models;

a call table storing the relative locations of said integrated circuit models for instant recall and execution;

a netlist transfer table for specifying the transfer of signals within said signal table corresponding to the signal distribution of the electronic circuit being designed;

said simulating means including processing means for producing, updating and storage in said signal table, said call table and said netlist transfer table;

initializing means for initializing said signal in said table;

said simulating means performing a simulation cycle by executing values from said call table and said netlist transfer table;

said simulation means repeating the simulation cycle until said integrated circuit design being created achieves a stable state;

whereby functional models of an electronic circuit can be created and instantaneously tested.

2. The system according to claim 1 in which said simulation means determines a stable state by repeatedly comparing an updated signal table with the previously updated signal table until they are identical.

3. The system according to claim 2 including delay means and for delaying the next execution of a simulation from said call and transfer tables until the integrated circuit design being tested achieves a stable state.

4. The system according to claim 3 including propagation delay inserting means for inserting compensation for propagation delays in said integrated circuit design.

5. The system according to claim 4 in which said propagation delay inserting means comprises means for generating a quantized propagation delay table;

means for generating a table of randomly selected propagation delays;

delay setting means for setting said delay means according to the randomly selected propagation delays in said table; and

modifying means for modifying said call table with said propagation delays from said random propagation delay table.

6. The system according to claim 2 including rejection means for rejecting said integrated circuit design from further processing if more than a selected number of simulation cycles have occured without said integrated circuit design achieving a stable state.

7. The system according to claim 6 in which said rejecting means includes counting means counting the number of simulation cycles;

and means for stopping the simulation processing if the number of simulation cycles exceeds a predetermined number.

8. A method of designing a circuit and simulating operating comprising;

storing behavorial models of integrated circuit chips;

selecting one or more integrated circuit models from said storage means;

automatically drawing inputs and outputs to said selected integrated circuit models to produce integrated circuit design data;

simulating inputs and outputs to and from said integrated circuit design;

storing tables of electronic component specifications;

said tables including;

storing all inputs and outputs of said integrated circuit models in a signal table;

storing the relative locations of said integrated circuit models for instant recall and execution in a call table;

generating a netlist transfer table for specifying the transfer of signals within said signal table corresponding to the signal distribution of the electronic circuit being designed;

processing the inputs and outputs of said simulation for producing, updating and storage in said signal table, said call table and said netlist transfer table;

initializing said singal in said signal table;

performing a simulation cycle by executing values from said call table and said netlist transfer table;

repeating the simulation cycle until said integrated circuit design being created achieves a stable state;

whereby functional models of an electronic circuit can be created and instantaneously tested.

9. The method according to claim 8 in which said simulation processing determines a stable state by repeatedly comparing an updated signal table with the previously updated signal table until they are identical.

10. The method according to claim 9 including delaying the next execution of a simulation from said call and netlist transfer tables until the integrated circuit design being tested achieves a stable state.

11. The system according to claim 10 including inserting for propagation delays in said integrated circuit design.

12. The method according to claim 11 in which said inserting of said inserting for propagation delay comprises generating a quantized propagation delay table;

generating a table of randomly selected propagation delays;

setting delay means in said integrated circuit design according to the randomly selected propagation delays in said table; and

modifying said call table with said propagation delays from said random propagation delay table.

13. The method according to claim 12 including rejecting said integrated circuit design from further processing if more than a selected member of simulation cycles have occured without said integrated circuit design achieving a stable state.

14. The method according to claim 13 in which said rejection step includes counting the number of simulation cycles;

and stopping simulation processing if the number of simulation cycles exceeds a predetermined number.