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Transistor sizing system for integrated circuits

  • US 4,827,428 A
  • Filed: 11/15/1985
  • Issued: 05/02/1989
  • Est. Priority Date: 11/15/1985
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising memory elements, input ports, output ports and a plurality of active elements constructed in accordance with a layout arrangement where at least one of said output ports is a critical output port that develops output signals with a delay that essentially is at a preselected maximum level, where each of said critical output ports has an associated critical path that contains those of said active elements whose size variations affect the signal delay of said critical output, and wherein at least some of said active elements in said critical paths are at sizes greater than a minimum size, said active element sizes being selected such that reducing the size of any active element in said critical paths causes the signal delay of at least one of said critical output ports to exceed said preselected maximum delay.

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