Transistor sizing system for integrated circuits

• US 4,827,428 A
• Filed: 11/15/1985
• Issued: 05/02/1989
• Est. Priority Date: 11/15/1985
• Status: Expired due to Term

• Current Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Dunlop, Alfred E., Fishburn, John P.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Trans, V. N.
• Application Number:
  US06/798,557
• Time in Patent Office: 1,264 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 324/73 R, 324/73 AT
• US Class Current: 716/113
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06Q 10/04 Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem" market predictions or forecasting for commercial activities G06Q30/0202

Abstract

A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element'"'"'s size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path'"'"'s timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.

Claims

1. An integrated circuit comprising memory elements, input ports, output ports and a plurality of active elements constructed in accordance with a layout arrangement where at least one of said output ports is a critical output port that develops output signals with a delay that essentially is at a preselected maximum level, where each of said critical output ports has an associated critical path that contains those of said active elements whose size variations affect the signal delay of said critical output, and wherein at least some of said active elements in said critical paths are at sizes greater than a minimum size, said active element sizes being selected such that reducing the size of any active element in said critical paths causes the signal delay of at least one of said critical output ports to exceed said preselected maximum delay.

2. A method for altering a given layout of an integrated circuit comprising the steps of:

designating said given layout as the current layout;

performing a timing analysis of said current layout to identify and output port of said integrated circuit that has a slower response than all other output ports of said integrated circuit;

performing a sensitivity analysis on the identified output port to locate an active element of said integrated circuit whose change in size improves the speed of response of said identified output port by the greatest amount;

automatically altering the size of said located active element; and

designating the layout resulting from said altering as the current layout and reiterating through the steps of this method until preselected criteria are met.

3. The method of claim 2 wherein said circuit includes feedback.

4. The method of claim 2 wherein said circuit includes memory elements.

5. An integrated circuit having input ports, output ports, and active elements therebetween, embedded in a layout developed in accordance with a method comprising the steps of:

designating said given layout as the current layout;

performing a timing analysis of said current layout to identify an output port of said integrated circuit that has a slower response than all other output ports of said integrated circuit;

performing a sensitivity analysis on the identified output port to locate an active element of said integrated circuit whose change in size improves the speed of response of said identified output port by the greatest amount;

altering the size of said located active element; and

designating the layout resulting from said altering as the current layout and reiterating through the steps of this method until preselected criteria are met.

6. An integrated circuit having input ports, output ports, and active elements therebetween, embedded in a layout developed in accordance with a method comprising the steps of:

representing said active elements by a model characterized by a function that is convex in the neighborhood of the operating point of said active elements;

obtaining information of the output signal timing delay between all of said input ports and each of said output ports;

selecting an output port from said output ports that, in accordance with said step of obtaining information, develops an output signal that is delayed more than all other output signals of said output ports;

investigating a subset of said active elements to determine the effect of altering the size of an active element in said subset on the delay of the output signal of said selected output port;

modifying that active element which, in accordance with said step of investigating, is determined to have the greatest effect on improving said delay of the output signal of said selected output port; and

returning to said step of obtaining information unless said specified criteria are met.

7. A method for improving the layout design of an electronic circuit having input ports, output ports, and active elements therebetween, with respect fo specified criteria, comprising the steps of:

representing said active elements by a model characterized by a function that is convex in the neighborhood of the operating point of said active elements;

obtaining information of the output signal timing delay between all of said input ports and each of said output ports;

selecting an output port from said output ports that, in accordance with said step of obtaining information, develops an output signal that is delayed more than all other output signals of said output ports;

investigating a subset of said active elements to determine the effect of altering the size of an active element in said subset on the delay of the output signal of said selected output port;

modifying that active element which, in accordance with said step of investigating, is determined to have the greatest effect on improving said delay of the output signal of said selected output port; and

returning to said step of obtaining information unless said specified criteria are met.

8. The method of claim 7 wherein said active elements are MOS transistors.

9. The method of claim 7 wherein model characterizes the delay of said active elements by a function that is convex in the area of interest.

10. The method of claim 7 wherein said model is based on a distributed R and C representation of said active elements.

11. The method of claim 10 wherein said model represents delay through one of said active elements in accordance with the equation Ax+B/x+C, where A, B, and C are positive constants, x is a size attribute of said active element, and all other size attributes of other active elements in said circuit are held constant.

12. The method of claim 7, further comprising the step of initially assigning a minimum size to all of said transistors.

13. The method of claim 7, further comprising the step of sorting subnetworks of said electronic circuit and selecting the permutation of said subnetworks that most improves the performance of said circuit with respect to said specified criteria.

14. The method of claim 7 wherein said circuit is an MOS VLSI integrated circuit.

15. The method of claim 7 wherein said circuit includes memory elements and said output ports include the set of output signal lines of said circuit and signal lines applied to said memory elements.

16. The method of claim 7 wherein said step of returning includes a step of evaluating performance of said circuit, altered by said step of modifying, with respect to said specified criteria.

17. The method of claim 7 wherein said specified criterion is related to a delay value to be satisfied.

18. The method of claim 7 wherein said specified criterion is related to a circuit area value to be satisfied.

19. A system for altering the layout of at least a portion of an integrated circuit comprising:

first means, responsive to an applied design specification and to an activation signal from a sixth means, for developing information concerning relative time delays of output signals of said integrated circuit;

second means, responsive to said first means, for selecting an output of said integrated circuit that develops an output signal more slowly than other outputs of said integrated circuit;

third, responsive to said second means, means for identifying active elements of said integrated circuit whose size alterations affect the output signal delay of said selected output;

fourth means, responsive to said third means, for selecting an active element from among the ones singled out by said third means, said active element offering the largest improvement in speed of the signals of said selected output in response to an alteration in the size of said active element, and accordingly modifying the size of that active element;

fifth means, responsive to said fourth means, for updating said information concerning relative time delays, based on the size modifications called for by said fourth means; and

sixth means for passing an activation signal to said first means as long as specified criteria are not met.

20. The system of claim 19, further including seventh means, responsive to said sixth means for sorting subnetworks of said integrated circuit that are interconnected in series.