Digital circuit for simultaneously generating digital sine- and cosine-function values

• US 4,827,442 A
• Filed: 09/08/1987
• Issued: 05/02/1989
• Est. Priority Date: 09/11/1986
• Status: Expired due to Fees

• Current Assignee: Deutsche ITT Industries GmbH
• Original Assignee: Deutsche ITT Industries GmbH
• Inventors: Schemmann, Heinrich, Mehrgardt, Soenke
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Mai, Tan V.
• Application Number:
  US07/094,466
• Time in Patent Office: 602 Days
• Field of Search: 364/721, 364/718, 364/603, 364/817, 364/729
• US Class Current: 708/276
• CPC Class Codes: G06F 1/0342 for generating simultaneously two or more related waveforms, e.g. with different phase angles only
• CPC Class Codes: G06F 1/0353 by using symmetrical properties of the function, e.g. using most significant bits for quadrant control
• CPC Class Codes: H04N 9/643 Hue control means, e.g. flesh tone control

Abstract

This circuit simultaneously provides the sine- and cosine-function values for one and the same digital argument from any of the quadrants of the sine and cosine functions. Stored in the two halves of a read-only memory are the unsigned function values of the first half-quadrant of the cosine function in the direction of increasing arguments and of the second half-quadrant in the direction of decreasing arguments, respectively. The number of bits of the argument is greater than the number of bits of the function values, including the sign bit, by two. By skillful inversion of the addresses and the read-out function values using multiple-inverter blocks in conjunction with multiple-switch units sine- and cosine-function values can be generated for all four quadrants both in the one'"'"'s and in the two'"'"'s complement code. If the argument is formed by an accumulator fed with the frequency determining digital word, the digital circuit is a digital sine-/cosine-wave oscillator.

Claims

1. A digital circuit for simultaneously generating digital values of sine and cosine functions for a single digital argument representing a phase angle in any of the four quadrants of the sine and cosine functions, comprising:

a read-only memory having a first memory half which contains unsigned values for the cosine function in the first half-quadrant of the cosine function in the direction of increasing arguments and a second memory half which contains unsigned values for the cosine function in the second half-quadrant of the cosine function in the direction of decreasing arguments, said values in said first memory half corresponding to unsigned values for the sine function in the second half quadrant of the sine function in the direction of decreasing arguments and said values in said second memory half corresponding to unsigned values for the sine function in the first half-quadrant of the sine function in the direction of increasing arguments, said values of said cosine function having n bits, the digital arguments being present in the unsigned binary code, each of said digital arguments having m bits, wherein m is greater than n;

a first multiple inverter block having a plurality of inverters each of which is provided a respective bit signal of the m-3 least significant bits of a digital argument signal input to said digital circuit;

a first multiple switch unit having a first input coupled to receive the input of said first multiple inverter block, a second input coupled to receive the output of said first multiple inverter block, and a control input coupled to receive the third most significant bit signal of said digital argument signal, the output of said first multiple switch being connected to the address input of said first and second memory halves so that as said argument signal increases, the cosine function values in said first memory half are read out in decreasing order and the cosine function values in said second memory half are read out in increasing order;

a second multiple switch unit having a first input connected to the output of said first memory half and a second input connected to the output of said second memory half;

a third multiple switch unit having a first input connected to the output of said second memory half and a second input connected to the output of said first memory half;

a first exclusive-OR gate having a first input connected to receive the second most significant bit signal of said argument signal, a second input connected to receive the third most significant bit signal of said argument signal, and an output connected to the control inputs of said second and third multiple switch units;

a second multiple inverter block connected to the output of said second multiple switch unit;

a third multiple inverter block connected to the output of said third multiple switch unit;

a fourth multiple switch unit having a first input connected to the input of said second multiple inverter block and a second input connected to the output of said second multiple inverter block, the output of said fourth multiple switch unit providing an unsigned digital cosine value;

a fifth multiple switch unit having a first input connected to the input of said third multiple inverter block and a second input connected to the output of said third multiple inverter block, the output of said fifth multiple switch unit providing an unsigned digital sine value; and

a second exclusive-OR gate having a first input connected to receive the most significant bit signal of said argument signal, a second input connected to receive the second most significant bit signal of said argument signal, and an output which is connected to the control input of said fourth multiple switch unit and added as the sign bit to the output of said fourth multiple switch unit to form the signed cosine value in the one'"'"'s complement code, the most significant bit of said argument signal being supplied to the control input of said fifth multiple switch unit and added as the sign bit to the output of said fifth multiple switch unit to form the signed sine value in the one'"'"'s complement code.

2. The digital circuit as defined in claim 1, wherein the number of bits m of said argument exceeds the number of bits n of said function by two.

3. A digital circuit as defined in claim 1 or 2 wherein said digital circuit is implemented with monolithic integrated semiconductor technology.

4. A digital circuit for simultaneously generating digital values of sine and cosine functions for a single digital argument representing a phase angle in any of the four quadrants of the sine and cosine functions, comprising:

a read-only memory having a first memory half which contains unsigned values for the cosine function in the first half-quadrant of the cosine function in the direction of increasing arguments and a second memory half which contains unsigned values for the cosine function in the second half-quadrant of the cosine function in the direction of decreasing arguments, said values in said first memory half corresponding to unsigned values for the sine function in the second half quadrant of the sine function in the direction of decreasing arguments and said values in said second memory half corresponding to unsigned values for the sine function in the first half-quadrant of the sine function in the direction of increasing arguments, said values of said cosine function having n bits, the digital arguments being present in the unsigned binary code, each of said digital arguments having m bits, wherein m is greater than n;

a first multiple inverter block having a plurality of inverters each of which is provided a respective bit signal of the m-3 least significant bits of a digital argument signal input to said digital circuit;

a first multiple switch unit having a first input coupled to receive the input of said first multiple inverter block, a second input coupled to receive the output of said first multiple inverter block, and a control input coupled to receive the third most significant bit signal of said argument signal, the output of said first multiple switch being connected to the address input of said first and second memory halves so that as said argument signal increases, the cosine function values in said first memory half are read out in decreasing order and the cosine function values in said second memory half are read out in increasing order;

a second multiple switch unit having a first input connected to the output of said first memory half and a second input connected to the output of said second memory half;

a third multiple switch unit having a first input connected to the output of said second memory half and a second input connected to the output of said first memory half;

a first exclusive-OR gate having a first input connected to receive the second most significant bit signal of said argument signal, a second input connected to receive the third most significant bit signal of said argument signal, and an output connected to the control inputs of said second and third multiple switch units;

a second multiple inverter block connected to the output of said second multiple switch unit;

a third multiple inverter block connected to the output of said third multiple switch unit;

a fourth multiple switch unit having a first input connected to the input of said second multiple inverter block and a second input connected to the output of said second multiple inverter block, the output of said fourth multiple switch unit providing an unsigned digital cosine value;

a fifth multiple switch unit having a first input connected to the input of said third multiple inverter block and a second input connected to the output of said third multiple inverter block, the output of said fifth multiple switch unit providing an unsigned digital sine value;

a second exclusive-OR gate having a first input connected to receive the most significant bit signal of said argument signal, a second input connected to receive the second most significant bit signal of said argument signal, and an output which is connected to the control input of said fourth multiple switch unit, the most significant bit of said argument signal being supplied to the control input of said fifth multiple switch unit;

a first parallel half-adder circuit comprising a plurality of first half-adders, said first parallel half-adder circuit being connected to the output of said fourth multiple switch unit, the output of said second exclusive-OR gate being added as the sign bit to the output of said first parallel half-adder circuit to form the signed cosine value in two'"'"'s complement code; and

a second parallel half-adder circuit comprising a plurality of second half-adders, said second parallel half-adder circuit being connected to the output of said fifth multiple switch unit, the most significant bit signal of said argument signal being added as the sign bit to the output of said second parallel half-adder circuit to form the signed sine value in the two'"'"'s complement code.

5. A digital circuit as defined in claim 4, wherein:

said fourth multiple switch unit comprises a plurality of switches and said fifth multiple switch unit comprises a plurality of switches;

each of said first half-adders has a first input connected to a respective one of said switches of said fourth multiple switch unit;

the one of said first half-adders that receives the least significant bit output from said fourth multiple switch unit has a second input connected to receive the output of said second exclusive-OR gate, and each of the remaining of said first half-adders has a second input connected to receive a carry output from its adjacent first half-adder;

each of said second half-adders has a first input connected to a respective one of said switches of said fifth multiple switch unit; and

the one of said second half-adders that receives the least significant bit output from said fifth multiple switch unit has a second input connected to receive the most significant bit signal of said argument, and each of the remaining of said second half-adders has a second input connected to receive a carry output from its adjacent second half-adder.

6. A digital sine-/cosine-wave oscillator that generates sine and cosine functions, comprising:

a read-only memory having a first memory half which contains unsigned values for the cosine function in the first half-quadrant of the cosine function in the direction of increasing arguments and a second memory half which contains unsigned values for the cosine function in the second half-quadrant of the cosine function in the direction of decreasing arguments, said values in said first memory half corresponding to unsigned values for the sine function in the second half quadrant of the sine function in the direction of decreasing arguments and said values in said second memory half corresponding to unsigned values for the sine function in the first half-quadrant of the sine function in the direction of increasing arguments, said values of said cosine function having n bits, the digital arguments being present in the unsigned binary code, each of said digital arguments having m bits, wherein m is greater than n;

a digital accumulator for producing a digital argument signal, said digital accumulator having an input that receives a digital word which determines the frequency of said oscillator, the summation of said accumulator being controlled by a clock signal;

a first multiple inverter block connected to said accumulator, said first multiple inverter block having a plurality of inverters each of which is provided a respective bit signal of the m-3 least significant bits of said digital argument signal;

a first multiple switch unit having a first input coupled to receive the input of said first multiple inverter block, a second input coupled to receive the output of said first multiple inverter block, and a control input coupled to receive the third most significant bit signal of said argument signal, the output of said first multiple switch being connected to the address input of said first and second memory halves so that as said argument signal increases, the cosine function values in said first memory half are read out in decreasing order and the cosine function values in said second memory half are read out in increasing order;

a second multiple switch unit having a first input connected to the output of said first memory half and a second input connected to the output of said second memory half;

a third multiple switch unit having a first input connected to the output of said second memory half and a second input connected to the output of said first memory half;

a first exclusive-OR gate having a first input connected to receive the second most significant bit signal of said argument signal, a second input connected to receive the third most significant bit signal of said argument signal, and an output connected to the control inputs of said second and third multiple switch units;

a second multiple inverter block connected to the output of said second multiple switch unit;

a third multiple inverter block connected to the output of said third multiple switch unit;

a fourth multiple switch unit having a first input connected to the input of said second multiple inverter block and a second input connected to the output of said second multiple inverter block, the output of said fourth multiple switch unit providing an unsigned digital cosine value;

a fifth multiple switch unit having a first input connected to the input of said third multiple inverter block and a second input connected to the output of said third multiple inverter block, the output of said fifth multiple switch unit providing an unsigned digital sine value; and

a second exclusive-OR gate having a first input connected to receive the most significant bit signal of said argument signal, a second input connected to receive the second most significant bit signal of said argument signal, and an output which is connected to the control input of said fourth multiple switch unit and added as the sign bit to the output of said fourth multiple switch unit to form the signed cosine value in the one'"'"'s complement code, the most significant bit of said argument signal being supplied to the control input of said fifth multiple switch unit and added as the sign bit to the output of said fifth multiple switch unit to form the signed sine value in the one'"'"'s complement code.

8. An oscillator as defined in claim 6 or 7 additionally comprising an adder connected between said accumulator and said first multiple inverter block, said adder having an input connected to receive a digital word representing a phase offset to be added to the argument signal output of said accumulator.

9. An oscillator as defined in claim 8 wherein said digital word applied to the input of said adder represents the tint phase of the chroma signal in a digital color television receiver and is supplied to said adder during the keying pulse.

7. A digital sine-/cosine-wave oscillator that generates sine and cosine functions, comprising:

a read-only memory having a first memory half which contains unsigned values for the cosine function in the first half-quadrant of the cosine function in the direction of increasing arguments and a second memory half which contains unsigned values for the cosine function in the second half-quadrant of the cosine function in the direction of decreasing arguments, said values in said first memory half corresponding to unsigned values for the sine function in the second half quadrant of the sine function in the direction of decreasing arguments and said values in said second memory half corresponding to unsigned values for the sine function in the first half-quadrant of the sine function in the direction of increasing arguments, said values of said cosine function having n bits, the digital arguments being present in the unsigned binary code, each of said digital arguments having m bits, wherein m is greater than n;

a digital accumulator having an input that receives a digital word which determines the frequency of said oscillator, the summation of said accumulator being controlled by a clock signal, the output of said accumulator being a digital argument signal that represents an angle;

a first multiple inverter block coupled to said accumulator, said first multiple-inverter block having a plurality of inverters each of which is provided a respective bit signal of the m-3 least significant bits of said digital argument signal;

a first multiple switch unit having a first input coupled to receive the input of said first multiple inverter block, a second input coupled to receive the output of said first multiple inverter block, and a control input coupled to receive the third most significant bit signal of said argument signal, the output of said first multiple switch being connected to the address input of said first and second memory halves so that as said argument signal increases, the cosine function values in said first memory half are read out in decreasing order and the cosine function values in said second memory half are read out in increasing order;

a second multiple switch unit having a first input connected to the output of said second memory half and a second input connected to the output of said first memory half;

a third multiple switch unit having a first input connected to the output of said second memory half and a second input connected to the output of said first memory half;

a first exclusive-OR gate having a first input connected to receive the second most significant bit signal of said argument signal, a second input connected to receive the third most significant bit signal of said argument signal, and an output connected to the control inputs of said second and third multiple switch units;

a second multiple inverter block connected to the output of said second multiple switch unit;

a third multiple inverter block connected to the output of said third multiple switch unit;

a fourth multiple switch unit having a first input connected to the input of said second multiple inverter block and a second input connected to the output of said second multiple inverter block, the output of said fourth multiple switch unit providing an unsigned digital cosine value;

a fifth multiple switch unit having a first input connected to the input of said third multiple inverter block and a second input connected to the output of said third multiple inverter block, the output of said fifth multiple switch unit providing an unsigned digital sine value;

a second exclusive-OR gate having a first input connected to receive the most significant bit signal of said argument signal, a second input connected to receive the second most significant bit signal of said argument signal, and an output which is connected to the control input of said fourth multiple switch unit, and the most significant bit of said argument signal being supplied to the control input of said fifth multiple switch unit;

a first parallel half-adder circuit comprising a plurality of first half-adders, said first parallel half-adder circuit being connected to the output of said fourth multiple switch unit, the output of said second exclusive-OR gate being added as the sign bit to the output of said first parallel half-adder circuit to form the signed cosine value in two'"'"'s complement code; and

a second parallel half-adder circuit comprising a plurality of second half-adders, said second parallel half-adder circuit being connected to the output of said fifth multiple switch unit, the most significant bit signal of said argument signal being added as the sign bit to the output of said second parallel half-adder circuit to form the signed sine value in the two'"'"'s complement code.

10. A digital circuit for simultaneously generating digital values of sine and cosine functions for a single digital argument comprising m bits that represent a phase angle from any of the four quadrants of the sine and cosine functions, comprising:

a read-only memory having a first memory half which contains unsigned values for the cosine function in the first half-quadrant of the cosine function in the direction of increasing arguments and a second memory half which contains unsigned values for the cosine function in the second half-quadrant of the cosine function in the direction of decreasing arguments, said values in said first memory half corresponding to unsigned values for the sine function in the second half quadrant of the sine function in the direction of decreasing arguments and said values in said second memory half corresponding to unsigned values for the sine function in the first half-quadrant of the sine function in the direction of increasing arguments, said values of said cosine function having n bits, wherein m is greater than n, the digital arguments being present in the unsigned binary code, said read-only memory addressable by the m-3 least significant bits of said argument to provide a pair of digital output values corresponding to the first half-quadrant of the cosine function and the second half-quadrant of the cosine function;

a function selection circuit comprising a plurality of switches and complementing circuits and controlled by the most significant three of said m bits of said argument, said most significant three bits providing one of eight encoded digital values corresponding to the eight half-quadrants of the sine-and cosine-functions, said selection circuit responsive to said eight encoded digital values to;

selectively address said read-only memory with either said m-3 least significant bits or the complement of said m-3 least significant bits;

select the digital outputs of one of the first memory half to provide an intermediate cosine function and select the digital outputs of the other memory half to provide an intermediate sine function;

selectively complement said intermediate cosine function to provide said cosine function output; and

selectively complement said intermediate sine function to provide said sine-function output.