Transmitting a digital signal and an additional signal

• US 4,827,475 A
• Filed: 07/02/1984
• Issued: 05/02/1989
• Est. Priority Date: 06/22/1984
• Status: Expired due to Fees

• Current Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Grover, Wayne D., Munter, Ernst A.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/626,895
• Time in Patent Office: 1,765 Days
• Field of Search: 370/110.1, 370/111, 370/18, 370/110.4, 371/52, 341/55, 341/60
• US Class Current: 370/527
• CPC Class Codes: H04B 17/0087 using auxiliary channels or channel simulators
• CPC Class Codes: H04J 3/12 Arrangements providing for calling or supervisory signals

Abstract

A digital signal, such as a t.d.m. PCM signal, is redundantly encoded in that sequences of n bits of the signal are transmitted as sequences of m bits, where m>n. Different sets of m-bit sequences are used to transmit the n-bit sequences in dependence upon the state of an additional signal, which may be a superframe indication signal. At a receiver, the digital signal and additional signal are reproduced. In the described embodiment =n+2, providing further redundancy to facilitate providing such desirable transmission code properties as maintaining d.c. balance and detecting errors on the transmission link.

Claims

1. A method of transmitting a digital signal, comprising n-bit sequences, and an additional signal, comprising the steps of:

providing first and second sets of m-bit sequences, where m>

n, each of said first and second sets having at least as many different m-bit sequences as there are different n-bit sequences;

converting each n-bit sequence of the digital signal into a respective m-bit sequence of the first set when the additional signal has a first state;

converting each n-bit sequence of the digital signal into a respective m-bit sequence of the second set when the additional signal has a second state; and

transmitting the m-bit sequences.

2. A method as claimed in claim 1 wherein m>

=n+2.

3. A method as claimed in claim 1 wherein at least one of the first and second sets of m-bit sequences comprises 2ⁿ m-bit sequences having, on average, equal numbers of binary ones and zeros.

4. A method as claimed in claim 1 wherein at least one of the first and second sets of m-bit sequences comprises 2ⁿ +p m-bit sequences, p being an integer, 2p of the sequences having, on average, equal numbers of binary ones and zeros.

5. A method as claimed in claim 4 wherein m is even, and each of the remaining 2ⁿ -p m-bit sequences has equal numbers of binary ones and zeros.

6. A method as claimed in claim 5 wherein said 2p of the m-bit sequences comprise a first group of p m-bit sequences each having more binary ones than zeros and a second group of p m-bit sequences each having more binary zeros than ones, m-bit sequences from said first and second groups being used alternately for the transmission of p of said n-bit sequences.

7. A method as claimed in claim 3 wherein n=10 and m=12.

8. A method of communicating a digital signal and an additional signal, comprising:

transmitting said signals by the method of claim 6;

receiving the transmitted m-bit sequences;

converting each received m-bit sequence in the first set into the respective n-bit sequence and a first state of a reproduced additional signal;

converting each received m-bit sequence in the second set into the respective n-bit sequence and a second state of the reproduced additional signal; and

producing an error indication in response to any other received m-bit sequence.

9. A method as claimed in claim 1 wherein the digital signal comprises a plurality of n-bit channels which are time division multiplexed in frames and superframes, and wherein the additional signal comprises a frame and/or superframe indication signal.

10. Apparatus for transmitting a digital signal, comprising n-bit sequences, and an additional signal, comprising:

means for storing first and second sets of m-bit sequences, where m>

n, each of said first and second sets having at least as many different m-bit sequences as there are different n-bit sequences;

means for addressing the storing means with each n-bit sequence of the digital signal and with the additional signal to supply from the storing means a respective m-bit sequence of the first set when the additional signal has a first state and a respective m-bit sequence of the second set when the additional signal has a second state; and

means for transmitting the m-bit sequences.

11. Apparatus as claimed in claim 10 wherein the storing means comprises means for storing and supplying, with each of said m-bit sequences, at least one additional bit, the apparatus including means responsive to the at least one additional bit supplied from the storing means with each m-bit sequence for addressing respective parts of the storing means with said digital and additional signals.

12. Apparatus as claimed in claim 10 wherein the storing means comprises a ROM (read-only memory).

13. Apparatus as claimed in claim 10 and including means for converting each m-bit sequence from a parallel sequence supplied from the storing means into a serial sequence for transmission.

14. Apparatus for communicating a digital signal and an additional signal, comprising apparatus as claimed in claim 10 for transmitting said signals, and apparatus for receiving the transmitted m-bit sequences, the receiving apparatus comprising:

storage means for storing, in respect of at least each of the m-bit sequences in the first and second sets, the respective n-bit sequence and the respective state of the additional signal; and

means for addressing the storage means with each received m-bit sequence to supply from the storage means a reproduced digital signal and a reproduced additional signal.

15. Apparatus as claimed in claim 14 wherein there are more m-bit sequences than are in said first and second sets, the apparatus including means responsive to each received m-bit sequence which is not in said sets for producing an error signal.

16. Apparatus as claimed in claim 14 wherein the means for addressing the storage means comprises converting means for converting each m-bit sequence from a serially received sequence into a parallel sequence for addressing the storage means.

17. Apparatus as claimed in claim 16 wherein the storage means comprises means for storing and producing an error signal in respect of each received m-bit sequence which is not in said sets.

18. Apparatus as claimed in claim 17 and including means responsive to the error signal for controlling the converting means.