Multilevel integrated circuits employing fused oxide layers

• US 4,829,018 A
• Filed: 06/27/1986
• Issued: 05/09/1989
• Est. Priority Date: 06/27/1986
• Status: Expired due to Term

• Current Assignee: Legion Advances LLC (Intellectual Ventures LLC)
• Original Assignee: Sven E. Wahlstrom
• Inventors: Wahlstrom, Sven E.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Wilczewski, M.
• Application Number:
  US06/879,738
• Time in Patent Office: 1,047 Days
• Field of Search: 357/75, 148/DIG. 12, 148/DIG. 135, 148/DIG. 164, 156/633, 156/657, 156/653, 437/974, 437/984, 437/40, 437/51, 437/83, 437/84, 437/225, 437/208, 437/915
• US Class Current: 438/154
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/135 Removal of substrate
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

A multilevel semiconductor integrated circuit is fabricated by providing a plurality of substrates having an epitaxial layer on one surface and a silicon oxide layer on the surface of the epitaxial layer. The substrates are sequentially stacked with the silicon oxide layers in contact and fused together. One substrate is retained as a support, and other substrates are removed by etching after the fusion of the silicon oxide layers, thereby leaving only the stacked epitaxial layers separated by silicon oxide. The stacked structure facilitates the vertical fabrication of CMOS transistor pairs sharing a common gate electrode in an epitaxial layer between the two transistors. Electrical isolation between the epitaxial layers is provided by the fused silicon oxide or by removing the silicon oxide and some of the silicon thereby forming a void between adjacent epitaxial layers. Circuit devices in the plurality of epitaxial layers are readily interconnected by forming conductive vias between the epitaxial layers.

Claims

1. In the fabrication of multilevel semiconductor integrated circuits, a method of forming devices in multilayers of silicon semiconductor material comprising the steps of

providing a first silicon semiconductor substrate having a first silicon compound dielectric layer on a surface of said substrate,

providing a second silicon semiconductor substrate having a first silicon epitaxial layer on one surface and a second silicon compound dielectric layer on a surface of said second epitaxial layer,

stacking said second silicon semiconductor substrate on said first silicon semiconductor substrate with said first and second silicon dielectric layers in contact,

fusing said dielectric layers together,

removing said second substrate by etching thereby leaving said first substrate as a support for said first epitaxial layer,

forming elements of an electrical device in said first epitaxial layer using photoresist masking,

providing a third silicon compound dielectric layer on the surface of said first epitaxial layer,

providing a third silicon semiconductor substrate having a second silicon epitaxial layer on one surface and a fourth silicon compound dielectric layer on the surface of said third epitaxial layer,

stacking said fourth dielectric layer on the third dielectric layer on said first epitaxial layer,

fusing said fourth dielectric layer to said third dielectric layer on said surface of said first epitaxial layer,

removing said third silicon semiconductor substrate by etching thereby leaving said first substrate as a support for said first and second silicon epitaxial layers,

forming elements of an electrical device in said second epitaxial layer using photoresist masking and wherein a photomask is optically aligned by looking through said second epitaxial layer to alignment marks on said first epitaxial layer, and

providing conductive vias between said first epitaxial layer and said second epitaxial layer for interconnecting electrical components in said first and second epitaxial layers.

2. The method as defined by claim 1 and further including the steps of

providing a fifth silicon compound dielectric layer on the surface of said second silicon epitaxial layer,

providing a fourth silicon semiconductor substrate having a third silicon epitaxial layer on one surface and a sixth silicon compound dielectric layer on a surface of said third epitaxial layer,

stacking said fourth semiconductor substrate and said third epitaxial layer on said second epitaxial layer with said fifth and sixth dielectric layers in contact,

fusing said fifth and sixth dielectric layers together,

removing said fourth substrate by etching thereby leaving said third epitaxial layer,

forming elements of an electrical device in said third epitaxial layer using photoresist masking and wherein a photomask is optically aligned by looking through said third epitaxial layer to alignment marks after fusing said third epitaxial layer to said second epitaxial layer,

providing conductive vias between said second epitaxial layer and said third epitaxial layer,

forming a source and a drain of a first field effect transistor in said first epitaxial layer,

forming a source and a drain of a second field effect transistor in said third epitaxial layer, and

forming a gate electrode in said second epitaxial layer for said first and second field effect transistors, said first and second field effect transistors forming a CMOS transistor pair.