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Multilevel integrated circuits employing fused oxide layers

  • US 4,829,018 A
  • Filed: 06/27/1986
  • Issued: 05/09/1989
  • Est. Priority Date: 06/27/1986
  • Status: Expired due to Term
First Claim
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1. In the fabrication of multilevel semiconductor integrated circuits, a method of forming devices in multilayers of silicon semiconductor material comprising the steps ofproviding a first silicon semiconductor substrate having a first silicon compound dielectric layer on a surface of said substrate,providing a second silicon semiconductor substrate having a first silicon epitaxial layer on one surface and a second silicon compound dielectric layer on a surface of said second epitaxial layer,stacking said second silicon semiconductor substrate on said first silicon semiconductor substrate with said first and second silicon dielectric layers in contact,fusing said dielectric layers together,removing said second substrate by etching thereby leaving said first substrate as a support for said first epitaxial layer,forming elements of an electrical device in said first epitaxial layer using photoresist masking,providing a third silicon compound dielectric layer on the surface of said first epitaxial layer,providing a third silicon semiconductor substrate having a second silicon epitaxial layer on one surface and a fourth silicon compound dielectric layer on the surface of said third epitaxial layer,stacking said fourth dielectric layer on the third dielectric layer on said first epitaxial layer,fusing said fourth dielectric layer to said third dielectric layer on said surface of said first epitaxial layer,removing said third silicon semiconductor substrate by etching thereby leaving said first substrate as a support for said first and second silicon epitaxial layers,forming elements of an electrical device in said second epitaxial layer using photoresist masking and wherein a photomask is optically aligned by looking through said second epitaxial layer to alignment marks on said first epitaxial layer, andproviding conductive vias between said first epitaxial layer and said second epitaxial layer for interconnecting electrical components in said first and second epitaxial layers.

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