Electronic semiconductor device for protecting integrated circuits against electrostatic discharges

• US 4,829,344 A
• Filed: 10/20/1986
• Issued: 05/09/1989
• Est. Priority Date: 10/29/1985
• Status: Expired due to Term

• Current Assignee: SGS Microeletrronica SpA (STMicroelectronics NV)
• Original Assignee: SGS Microeletrronica SpA (STMicroelectronics NV)
• Inventors: Ferrari, Paolo, Bertotti, Franco
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Mintel, William A.
• Application Number:
  US06/921,071
• Time in Patent Office: 932 Days
• Field of Search: 357/13, 357/58, 357/33, 357/13 U, 357/13 Z, 357/13 R, 357/23.13
• US Class Current: 257/546
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

This electronic semiconductor device for protecting integrated circuits against electrostatic discharges has a minimal bulk, can withstand high damaging voltages and be produced during the same production phases as the integrated circuit to be protected. The device comprises a pair of diodes connected back to back, arranged between an input of the integrated circuit to be protected and the ground line, with the cathodes connected together and formed by a single semiconductor layer and the anodes formed in a single process phase by employing top-bottom production techniques.

Claims

1. An electronic semiconductor device for protecting an integrated circuit against electrostatic discharges comprising two diodes connected back to back, said diodes comprising

a substrate of a first conductivity type,

an epitaxial layer of a second conductivity type extending between an outer face of the device and said substrate,

a buried layer having a second conductivity type, substantially opposite to said first conductivity type, said buried layere extending between said substrate and said epitaxial layer,

first and second simultaneously implanted regions of said first conductivity type substantially including said first conductivity type substrate, said first and second regions being highly-doped with respect to said substrate and extending in said substrate and in said epitaxial layer in contact with said buried layer on two opposite sides thereof, thereby forming with said buried layer two P-N junctions,

and a connection zone of said first conductivity type, which is highly-doped with respect to said substrate, and substantially includes said first conductivity type substrate, said connection zone extending through said epitaxial layer, between said outer face of said device and said first region.

2. A device according to claim 1 comprising two back to back connected diodes, said diodes comprising said buried layer, and said first and second regions, said first and second regions thereby defining two P-N junctions with said buried layer, said first region being electrically connected to a voltage reference line, and said second region being connected to an input terminal of an integrated circuit to be protected.

3. A device according to claim 1, wherein said device is arranged below an input pad of said integrated circuit to be protected.