Charge redistribution A/D converter with reduced small signal error

• US 4,831,381 A
• Filed: 08/11/1987
• Issued: 05/16/1989
• Est. Priority Date: 08/11/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hester, Richard K.
• Primary Examiner(s): Roskoski, Bernard
• Application Number:
  US07/084,277
• Time in Patent Office: 644 Days
• Field of Search: 340/347 AD, 340/347 DA, 340/347 C, 340/347 NT
• US Class Current: 341/172
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

An A/D converter utilizing a charge redistribution scheme includes a single ended comparator and associated therewith a capacitor array of binary weighted capacitors. The input signal is sampled with the input of the comparator disposed at a point midway between ground and a unipolar reference voltage. The bottom plates of the capacitors in the hold mode are then disposed at the midpoint of the reference signal. In the redistribution mode, the value of the bits is determined by switching the bottom plates of the capacitors between the midpoint of the reference voltage and either ground or the full value of the reference voltage. The input signal during sampling is attenuated by sampling it onto only one-half of the array.

Claims

1. A redistribution A/D converter, comprising:

a capacitor array of binary weighted capacitors, each of said capacitors having a lower and an upper plate with the upper plate of each of said capacitors being common;

sample means for sampling an input analog voltage on said capacitor array such that charge is stored in said capacitor said sample means comprising a plurality of switches, each of said switches associated with the bottom plate of one of said capacitors and operable during sampling by said sampling means, the one of said switches associated with the largest of the capacitors in said capacitor array operable to connect the bottom plate thereof to said predetermined reference voltage, and the remaining of said switches associated with the remaining of said capacitors in said array operable to connect the output of said capacitors to said input analog voltage such that the input voltage is attenuated by a factor of two, said sample means operable to selectively connect the upper plates of said capacitors to said predetermined hold reference voltage during sampling by said sample means;

hold means for connecting the lower plates of said capacitors to a predetermined hold reference voltage during a predetermined hold time after sampling by said sample means, said predetermined hold reference voltage being between ground and a unipolar reference voltage, such that the voltage on the upper plates of each of said capacitors is equal and offset from said hold reference voltage; and

redistribution means for redistributing the charge in said capacitor array after the voltage on the upper plates of said capacitors is offset by said hold means by connecting the bottom plate of select ones of said capacitors to either said unipolar reference, said predetermined hold reference voltage or ground in accordance with a predetermined successive approximation technique such that the voltage on the upper plate of said capacitors is equal to said predetermined hold reference voltage after all of said capacitors have the bottom plates thereof selectively connected.

2. A redistribution A/D converter, comprising:

a capacitor array of binary weighted capacitors, each of said capacitors having a lower and an upper plate with the upper plate of each of said capacitors being common;

sample means for sampling an input analog voltage on said capacitor array such that charge is stored in said capacitors proportional to said input analog voltage;

hold means for connecting the lower plates of said capacitors to a predetermined hold reference voltage during a predetermined hold time after sampling by said sample means, said predetermined hold reference voltage being between ground and a unipolar reference voltage, such that the voltage on the upper plates of each of said capacitors is equal and offset from said hold reference voltage; and

redistribution means for redistributing the charge in said capacitor array after the voltage on the upper plates of said capacitors is offset by said hold means by connecting the bottom plate of select ones of said capacitors to either said unipolar reference, said predetermined hold reference voltage or ground in accordance with a predetermined successive approximation technique such that the voltage on the upper plate of said capacitors is equal to said predetermined hold reference voltage after all of said capacitors have the bottom plates thereof selectively connected, said redistribution means comprising sign means for determining the sign of the input analog signal and generating a sign bit indicative of the sign of the input analog signal, a plurality of redistribution switches associated with the bottom plates of said capacitors and each operable to connect the bottom plate of said associated capacitor to either said unipolar reference voltage or said hold reference voltage when said sign bit indicates a positive input analog signal, or to either ground or said unipolar reference voltage when said sign bit indicates a negative input analog signal, a comparator for comparing the voltage on the upper plate of said capacitors with said hold reference voltage to determine if the voltage on the upper plates of said capacitors is higher or lower than said hold reference voltage, and successive approximation circuitry for controlling said plurality of redistribution swithces for controlling the operation of said redistribution switches and the orientation thereof in accordance with said predetermined successive approximation technique to redistribute the charge on the said capacitors until the voltage on the upper plates thereof is approximately equal to said hold reference voltage.

3. A redistribution A/D converter, comprising:

a capacitor array of binary weighted capacitors, each of said capacitors having an upper plate and a lower plate with the upper plates of each of said capacitors being common;

a unipolar reference voltage;

a midpoint reference voltage equal to one-half of said unipolar reference voltage;

a ground reference voltage;

first switch means for connecting the common upper plate of each of said capacitors to ground and interfacing said lower plates to a sampled input analog voltage to impress a voltage proportional to said input analog voltage across said capacitors in said array, said first switch means operable in a sample mode;

sign means for sampling the analog input voltage to determine whether the analog input voltage is positive or negative and generating a sign bit having first and second logic states indicative of whether the analog input voltage is positive or negative, respectively;

second switch means for connecting the lower plates of said capacitors in said array to said midpoint voltage, said second switch means operable in a hold mode after sampling in the sample mode;

third switch means operable in a redistribution mode after operation of said second switch means in said hold mode, said third switch means operable to connect the lower plates of each of said capacitors to either said reference voltage or said midpoint reference voltage in response to said sign bit indicating a positive analog input voltage, and operable to connect the lower plates of said capacitors to either said midpoint reference voltage or ground in response to said sign bit indicating a negative input analog voltage;

a comparator for comparing the voltage on the common upper plate of said capacitors with said midpoint reference voltage to determine if the voltage on the common upper plates is greater or less than said midpoint reference voltage and outputting a corresponding output signal; and

successive approximation means operable to control said third switch means in said redistribution mode in accordance with a predetermined successive approximation technique to distribute the charge in the array until the voltage on said common upper plate is approximately equal to said midpoint reference voltage.

4. The A/D converter of claim 3 wherein said first switch means is operable in the sample mode to connect the lower plate of the most significant bit capacitor to said reference voltage and to connect the lower plate of the remaining of said capacitors to the sample input analog voltage such that the sampled input analog signal is sampled on only one-half of the capacitance in said array.

5. The A/D converter of claim 3 wherein said second switch means comprises a plurality of switches, each switch associated with the lower plate of one of said capacitors in said array and connected on one end thereof to the lower plate of the associated one of said capacitors and to the other end thereof to said midpoint reference voltage.

6. The A/D converter of claim 3 wherein said third switch means comprises:

multiplexer means for receiving on the input thereof said reference voltage, said midpoint reference voltage and ground and for outputting either said midpoint reference voltage and said reference voltage in response to said sign bit indicating a positive input analog voltage, and outputting said midpoint reference voltage and ground in response to said sign bit indicating a negative analog voltage; and

a plurality of switches each associated with one of said capacitors in said array and each operable to connect the lower plate of said associated capacitor with either of the two outputs from said multiplexer means under control of said successive approximation means.

7. A method for converting analog signals to digital signals, comprising:

providing a capacitor array of binary weighted capacitors with each of the capacitors having a common upper plate and an individual lower plate;

sampling an input analog signal onto the array, said step of sampling comprising connecting the lower plates of the capacitors representing one-half of the capacitance in the array to the sampled input analog voltage and the upper plates thereof to ground, with the upper plates of the remaining capacitors in the array connected to ground and the lower plates thereof connected to the unipolar reference voltage;

disposing the lower plate of the capacitors at a predetermined hold reference voltage having a voltage between ground and a unipolar reference voltage, such that the voltage across each of the capacitors is equal and proportional to the sampled input analog voltage; and

redistributing the charge on the capacitors in the array by connecting the bottom plates on select ones of the capacitors to either the unipolar reference, the predetermined hold reference voltage or ground in accordance with a predetermined successive approximation technique such that the voltage on the upper plate of the capacitors is equal to the predetermined hold reference voltage.

8. A method for converting analog signals to digital signals, comprising:

providing a capacitor array of binary weighted capacitors with each of the capacitors having a common upper plate and an individual lower plate;

sampling an input analog signal onto the array;

disposing the lower plate of the capacitors at a predetermined hold reference voltage having a voltage between ground and a unipolar reference voltage, such that the voltage across each of the capacitors is equal and proportional to the sampled input analog voltage; and

redistributing the charge on the capacitors in the array by connecting the bottom plates on select ones of the capacitors to either the unipolar reference, the predetermined hold reference voltage or ground in accordance with a predetermined successive approximation technique such that the voltage on the upper plate of the capacitors is equal to the predetermined hold reference voltage, said step of redistributing the charge in the capacitors comprising determining the sign of the analog input voltage and generating a sign bit indicative of the sign of the input analog signal, selectively connecting the bottom plate of each of the capacitors in the array to either the unipolar reference voltage or the hold reference voltage when the sign bit indicates a positive input analog signal, or selectively connecting the bottom plate of each of the capacitors to the hold reference voltage or ground when the sign bit indicates a negative input signal, comparing the voltage on the upper plate of the capacitors with the hold reference voltage to determine if the voltage on the upper plate is higher or lower than the hold reference voltage, and applying a successive approximation technique responsive to the output comparison value to control the selective connection of the bottom plates of the capacitors to either the unipolar reference voltage or ground in accordance with the successive approximation technique.

9. A redistribution A/D converter, comprising:

a capacitor array of binary weighted capacitors, each of said capacitors having a lower and an upper plate with the upper plate of each of said capacitors being common;

sampling circuitry operable for sampling an input analog voltage on said capacitor array such that charge is stored in said capacitor proportional to said input analog voltage said sampling circuitry comprising a plurality of switches, each of said switches associated with the bottom plate of one of said capacitors and operable during sampling by said sampling circuitry, the one of said switches associated with the largest of the capacitors in said capacitor array operable to connect the bottom plate thereof to said predetermined reference voltage, and the remaining of said switches associated with the remaining of said capacitors in said array operable to connect the output of said capacitors to said input analog voltage such that the input voltage is attenuated by a factor of two, said sampling circuitry operable to selectively connect the upper plates of said capacitors to said predetermined hold reference voltage during sampling by said sampling circuitry;

hold voltage circuitry operable for connecting the lower plates of said capacitors to a predetermined hold reference voltage during a predetermined hold time after sampling by said sampling circuitry, said predetermined hold reference voltage being between ground and a unipolar reference voltage, such that the voltage on the upper plates of each of said capacitors is equal and offset from said hold reference voltage; and

redistribution circuitry operable for redistributing the charge in said capacitor array after the voltage on the upper plates of said capacitors is offset by said hold voltage circuitry by connecting the bottom plate of select ones of said capacitors to either said unipolar reference, said predetermined hold reference voltage or ground in accordance with a predetermined successive approximation technique such that the voltage on the upper plate of said capacitors is equal to said predetermined hold reference voltage after all of said capacitors have the bottom plates thereof selectively connected.

10. A redistribution A/D converter, comprising:

a capacitor array of binary weighted capacitors, each of said capacitors having a lower and an upper plate with the upper plate of each of said capacitors being common;

sample circuitry operable for sampling an input analog voltage on said capacitor array such that charge is stored in said capacitors proportional to said input analog voltage;

hold voltage circuitry operable for connecting the lower plates of said capacitors to a predetermined hold reference voltage during a predetermined hold time after sampling by said sampling circuitry, said predetermined hold reference voltage being between ground and a unipolar reference voltage, such that the voltage on the upper plates of each of said capacitors is equal and offset from said hold reference voltage; and

redistribution circuitry operable for redistributing the charge in said capacitor array after the voltage on the upper plates of said capacitors is offset by said hold voltage circuitry by connecting the bottom plate of select ones of said capacitors to either said unipolar reference, said predetermined hold reference voltage or ground in accordance with a predetermined successive approximation technique such that the voltage on the upper plate of said capacitors is equal to said predetermined hold reference voltage after all of said capacitors have the bottom plates thereof selectively connected, said redistribution means comprising sign means for determining the sign of the input analog signal and generating a sign bit indicative of the sign of the input analog signal, a plurality of redistribution switches associated with the bottom plates of said capacitors and each operable to connect the bottom plate of said associated capacitor to either said unipolar reference voltage or said hold reference voltage when said sign bit indicates a positive input analog signal, or to either ground or said unipolar reference voltage when said sign bit indicates a negative input analog signal, a comparator for comparing the voltage on the upper plate of said capacitors with said hold reference voltage to determine if the voltage on the upper plates of said capacitors is higher or lower than said hold reference voltage, and successive approximation circuitry for controlling said plurality of redistribution switches for controlling the operation of said redistribution switches and the orientation thereof in accordance with said predetermined successive approximation technique to redistribute the charge on the said capacitors until the voltage on the upper plates thereof is approximately equal to said hold reference voltage.

11. A redistribution A/D converter, comprising:

a capacitor array of binary weighted capacitors, each of said capacitors having an upper plate and a lower plate with the upper plates of each of said capacitors being common;

a unipolar reference voltage;

a midpoint reference voltage equal to one-half of said unipolar reference voltage;

a ground reference voltage;

first switch for connecting the common upper plate of each of said capacitors to ground and interfacing said lower plates to a sampled input analog interfacing said lower plates to a sampled input analog voltage to impress a voltage proportional to said input analog voltage across said capacitors in said array, said first switch means operable in a sample mode;

sign determining circuit for sampling the analog input voltage to determine whether the analog input voltage is positive or negative and generating a sign bit having first and second logic states indicative of whether the analog input voltage is positive or negative, respectively;

second switch for connecting the lower plates of said capacitors in said array to said midpoint voltage, said second switch means operable in a hold mode after sampling in the sample mode;

third switch operable in a redistribution mode after operation of said second switch means in said hold mode, said third switch means operable to connect the lower plates of each of said capacitors to either said reference voltage or said midpoint reference voltage in response to said bit indicating a positive analog input voltage, said operable to connect the lower plates of said capacitors to either said midpoint reference voltage or ground in response to said bit indicating a negative input analog voltage;

a comparator for comparing the voltage on the common upper plate of said capacitors with said midpoint reference voltage to determine if the voltage on the common upper plates is greater or less than said midpoint reference voltage and outputting a corresponding output signal; and

successive approximation circuitry operable to control said third switch means in said redistribution mode in accordance with a predetermined successive approximation technique to distribute the charge in the array until the voltage on said common upper plate is approximately equal to said midpoint reference voltage.