Low voltage power down logic control circuit

• US 4,831,595 A
• Filed: 05/06/1987
• Issued: 05/16/1989
• Est. Priority Date: 05/06/1987
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Bone, Robert L.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US07/047,085
• Time in Patent Office: 741 Days
• Field of Search: 365/229
• US Class Current: 365/229
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A power down logic control circuit employing a diode and a capacitor to develop a voltage from a main power supply which normally holds a transistor in an "off" state. Upon disconnection of the main supply, the transistor switches "on" and activates a second transistor. Upon activation, the second transistor produces an inhibit signal to tri-state memory control circuitry and thereby preserve the memory data during transition to standby memory power provided by a lithium battery.

Claims

1. A control circuit for providing standby power to a memory circuit where primary power applied to said memory circuit is interrupted, said primary power being supplied by a primary power supply which supplies a primary voltage to said memory said control circuit, comprising:

standby power supply means coupled to said memory circuit for providing standby power to said memory circuit while primary power is interrupted to preserve information stored in said memory circuit;

voltage storage means coupled to said primary power for storing a voltage derived from said primary power supply; and

a first transistor having a base, emitter and collector, said emitter being connected to said voltage storage means, said base being connected to said primary power source; and

a second transistor having a base, emitter and collector, said base being connected to the collector of said second transistor, said emitter being connected to ground, and said output signal for interrupting the reading and writing operations in said memory circuit while said primary power is interrupted.

2. The control circuit of claim 1 wherein said first transistor comprises a NPN bipolar transistor.

3. The control circuit of claim 1 wherein said second transistor comprises a PNP bipolar transistor.

4. A circuit for a memory coupled by way of power line to a primary power source which supplies a source voltage, and to a standby power supply for providing a standby voltage to said memory when the source voltage is interrupted, said circuit comprising:

charge storage means coupled to said power source for storing a voltage derived from said power source, said charge storage means having a diode means and capacitor means connected together at a junction and between said power line and a ground voltage; and

switch means connected to said charge storage means, said power line, and said memory for responding to a change in the difference between the source voltage and the voltage stored in said charge storage means to generate an inhibit signal for provision to said memory.

5. The control circuit of claim 4 wherein said power source and standby power supply are direct current (D.C.) supplies.

6. The control circuit of claim 4 wherein said means for generating an inhibit signal includes first switch means for responding to the disconnection of said power source and a second switch means for generating said inhibit signal, said first switch means includes a transistor having its emitter connected to said junction.

7. The control circuit of claim 6 wherein said second switch means comprises a second transistor having its base connected to the collector of said first transistor.

8. The control circuit of claim 7 wherein said standby voltage is connected to said power line by means of a diode.

9. The control circuit of claim 7 further including a first resistance connected from the base of said first transistor to ground.

10. The control circuit of claim 9 further including a second resistance connected from the base of said second transistor to ground.

11. The control circuit of claim 10 wherein said inhibit signal is generating at the collector of said second transistor.

12. A circuit for controlling a memory circuit during disconnection of a main power supply coupled to said memory circuit, the memory circuit comprising a memory, a logic control circuit, first and second power supply lines coupled to said memory and logic control circuit, respectively, and a plurality of inhibit lines, the first and second power supply lines being normally supplied with power from the main power supply, said circuit comprising:

standby power supply means for supplying standby power to said first power supply line upon occurrence of said disconnection; and

switch means responsive to said disconnection of said main power supply for generating an inhibit signal on said inhibit lines for a selected time interval after said disconnection, said switch means comprising;

storage means for storing a voltage while said main power supply is connected said first and second supply lines;

a first transistor having its emitter connected to said storage means and its base connected to said main power supply; and

a second transistor having its base connected to the collector of said first transistor and its collector to said inhibit line said transistors maintaining an "off" state in response to the voltage stored by said storage means and for turning on and supplying said inhibit signal in response to said disconnection of said main power supply.

13. The power down logic control circuit of claim 12 wherein said storage means for developing and holding a voltage comprises:

a diode having an anode connected to said main power supply and a cathode; and

a capacitor means having a terminal connected to the emitter of said first transistor and to the cathode of said diode.

14. A circuit for providing standby power to a memory circuit when primary power applied to said memory circuit is interrupted, said circuit comprising:

standby power supply means coupled to said memory circuit for providing standby power to said memory circuit while primary power is interrupted to preserve information stored in said memory circuit;

voltage storage means coupled to said primary power supply for storing a voltage derived from said primary power supply; and

switching means coupled to said voltage storage means, said primary power supply and said memory circuit, for sensing the interruption of primary power supplied by said primary power supply and inhibiting reading and writing operations to said memory circuit while said primary power is interrupted, said switching means comprising;

first transistor means having a base, emitter and collector, said emitter being connected to said voltage storage means, said base being connected to said primary power source; and

second transistor means having a base, emitter and collector, said base being connected to the collector of said first transistor means, said emitter being connected to ground, and said collector being connected to said memory circuit, for providing an output signal which interrupts the reading and writing operations to said memory circuit while said primary power is interrupted.

15. A circuit for interconnecting a memory to a power source which supplies a source voltage, said circuit comprising:

a power line connectable to said power source;

a standby voltage supply connected to said power line;

charge storage means having a first terminal coupled to said power line for storing a voltage derived from said power source, said charge storage means having a second terminal connected to ground voltage; and

switch means connected to said charge storage means, to said power line and to said memory for responding to a change in the difference between the source voltage and the voltage stored in said charge storage means and for generating an inhibit signal which is provided to said memory, said switch means including first switch means for responding to the disconnection of said power source and second switch means for generating said inhibit signal.

16. A power-down circuit for controlling a memory circuit during disconnection of a main power supply coupled to said memory circuit, the memory circuit comprising a memory and a logic control circuit and having first and second power supply lines coupled to said memory and logic control circuit, respectively, and a plurality of inhibit lines, the first and second power supply lines being normally supplied with power from the main power supply, said circuit comprising:

standby power supply means for supplying standby power to said memory by way of said first power supply line upon occurrence of said disconnection of said main power supply; and

switch means responsive to said disconnection of said main power supply for generating an inhibit signal on said inhibit lines for a selected time interval after said disconnection, said switch means comprising;

first transistor means having a base, emitter and collector, said emitter being connected to said first power supply line; and

second transistor means having a base, emitter and collector, said base being connected to the collector of said first transistor means, and said collector being connected to said inhibit lines.