EEPROM fabrication process

• US 4,833,096 A
• Filed: 01/19/1988
• Issued: 05/23/1989
• Est. Priority Date: 01/19/1988
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Chern, Geeng-Chuan, Huang, John Y.
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US07/145,467
• Time in Patent Office: 490 Days
• Field of Search: 437/43, 437/52, 437/34, 437/240, 437/27, 437/28, 437/29, 437/30, 437/45, 437/70, 437/195, 437/200, 357/23.5, 156/643, 156/644
• US Class Current: 438/201
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

An EEPROM fabrication process using N-well CMOS technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high-temperature drive-in and oxidation cycle with a 1000 Å to 2500 Å thick nitride mask covering device areas. The floating gate stack with tunneling window is formed by implanting a first species of N-type impurity, forming a first gate oxide layer, defining a window in the oxide layer over the implant, implanting a second species of N-type impurity through the window, regrowing a thin oxide layer 70 Å to 90 Å thick in a window, depositing a first polysilicon layer having a thickness of between 2500 Å and 3400 Å, selectively removing the polysilicon and gate oxide layers to form a floating gate, growing a uniformly thick second oxide layer at 1,000° to 1,050° C. over both the substrate and floating gate, depositing a second polysilicon gate layer and selectively etching away the second polysilicon gate layer to form control gates. Metal coverage in the double layer of conductive lines is improved by rounding corners of glass by means of glass flow and re-flow, corners of intermetal layers by planarization and wet/dry etcing of the via holes, and corners of the first metal by means of wet/dry etching.

Claims

1. An EEPROM fabrication process comprising,

forming an N-well in a P-type wafer substrate,

forming N-channel and P-channel MOS devices on said substrate, said MOS devices having sources, drains and gates associated therewith, said P-channel MOS device being formed in said N-well,

forming an electrically-erasable and programmable memory cell on said substrate, said memory cell being formed with a floating gate disposed over an oxide layer including a thin-oxide window region,

depositing a boron and phosphorus doped silica glass layer covering said MOS devices and said memory cell, forming contact holes in said covering, and heating said glass layer covering to a flow temperature,

forming a first layer of conductive lines on said glass layer, said lines connecting to selected sources, drains and gates of said MOS devices and of said memory cell via said contact holes,

forming an insulative intermetal layer over said first layer of conductive lines, said intermetal layer being formed with a substantially planar surface and with via holes therein having rounded corners, and

forming a second layer of conductive lines on said intermetal layer, said lines of said second layer connecting to selected lines of said first layer through said via holes.

2. The process of claim 1 wherein forming said memory cell comprises,

implanting a first species of N-type impurity in said substrate,

thermally growing a first oxide layer on said substrate and defining a window therein over a portion of said first impurity implant,

implanting a second species of N-type impurity in said substrate through said window, said first and second species of N-type impurity being located in regions of said substrate which overlap under said window,

regrowing a thin oxide layer in said window to a thickness of 70 Å

to 90 Å

,

depositing a first polysilicon layer over said first oxide layer and said thin oxide layer, said first polysilicon layer having a thickness of 2500-3400 Å

,

selectively removing said first polysilicon layer and said first oxide layer to form a floating gate disposed over said first oxide layer including the thin-oxide window region,

thermally growing a second oxide layer over said floating gate and said wafer substrate, said second oxide layer being grown at a temperature of 1000°

C. to 1050°

C.,

depositing a second gate layer over said second oxide layer, and

selectively removing said second gate layer for defining N-channel device, P-channel device and memory cell device gates.

3. The process of claim 2 wherein said second gate layer is formed from polysilicon.

4. The process of claim 2 wherein said second gate layer is formed of a polysilicon and silicide sandwich.

5. The process of claim 1 wherein forming contact holes in said glass layer comprises selectively etching said glass layer over said selected sources, drains and gates, said heating of said wafer after said contact etch having the effect of smoothing out corners at the top of said contact holes.

6. The process of claim 1 wherein said boron and phosphorus doped silica glass has a concentration of 2.0 wt. % to 4.0 wt. % boron and 4 wt. % to 8 wt. % phosphorus, said glass having a flow temperature of approximately 900°

C. to 1000°

C.

7. The process of claim 1 wherein forming said insulative intermetal layer comprises,

depositing a layer of insulative material on said first layer of conductive lines,

etching back 60% to 90% of said insulative material,

re-depositing said insulative material to a thickness in a range from 6000 Å

to 14000 Å

, said redeposited material forming a substantially planar surface, and

selectively etching vias through said planar surface over said selected first conductive lines using a wet and dry etch.

8. An EEPROM fabrication process comprising,

forming an N-well in a P-type substrate,

defining N-channel and P-channel MOS devices on said substrate, said MOS devices having sources, drains and gates associated therewith, said P-channel MOS device being formed in said N-well,

forming an electrically-erasable and programmable memory cell on said substrate, said memory cell being formed with a floating gate disposed over an oxide layer, said oxide layer including a thin-oxide window region under said floating gate, wherein two species of N-type impurities are implanted in said substrate in overlapping regions under said floating gate, the regions overlapping under said window region for tunneling,

forming a glass layer over said devices on said substrate and forming contact holes with rounded corners therein, and

forming a first layer of conductive lines on said glass layer, said lines connecting to selected sources, drains and gates of said devices via said contact holes.

9. The process of claim 8 further comprising forming an insulative intermetal layer over said first layer of conductive lines with via holes therein, and forming a second layer of conductive lines on said intermetal layer, said lines of said second layer connecting to selected lines of said first layer through said via holes.

10. The process of claim 8 wherein said two species of N-type impurities implanted under said window region are phosphorus and arsenic.

11. The process of claim 8 wherein said oxide layer has a thickness in a range from 250 Å

to 750 Å and

said thin-oxide window region has a thickness in a range from 70 Å

to 90 Å

.

12. An EEPROM fabrication process comprising,

forming an N-well in a P-type substrate,

defining N-channel, P-channel and memory cell device areas in said substrate, said P-channel device areas being defined in said N-well,

forming N-channel stops and field oxide around said device areas,

implanting a first species of N-type impurity in a portion of each said memory cell device area in said substrate,

thermally growing a first oxide layer on said wafer substrate and defining a window therein over a portion of said first N-type impurity implant,

implanting a second species of N-type impurity in said substrate through said window, said first and second species of N-type impurity being located in regions of said substrate which overlap under said window,

regrowing a thin oxide layer in said window to a thickness of 70 Å

to 90 Å

,

depositing a first polysilicon layer over said first oxide layer and said thin oxide layer, said first polysilicon layer having a thickness of 2500 Å

to 3400 Å

,

selectively removing said first polysilicon layer and said first oxide layer from all areas of said wafer substrate except said memory cell device areas so as to form a floating gate disposed over said first oxide layer including the thin-oxide window region,

thermally growing a second oxide layer over said floating gate and said wafer substrate, said second oxide layer being grown at a temperature in the range from 1000°

C. to 1050°

C. to a thickness in a range from 320 Å

to 360 Å

,

introducing a threshold adjusting dopant into selected N-channel and P-channel device areas,

depositing a second gate layer over said second oxide layer,

selectively removing said second gate layer and said second oxide layer for defining N-channel device, P-channel device and memory cell device gates,

forming sources and drains for said devices,

depositing a glass layer over said devices on said wafer substrate and forming contact holes with rounded corners therein, and

forming a first layer of conductive lines on said glass layer, said lines connecting to selected sources, drains and gates of said devices via said contact holes.

13. The process of claim 12 further comprising forming an insulative intermetal layer over said first layer of conductive lines, said intermetal layer being formed with via holes therein having rounded corners, and forming a second layer of conductive lines on said intermetal layer, said lines of said second layer connecting to selected lines of said first layer through said via holes.

14. The process of claim 13 wherein

(a) depositing said glass layer and forming contact holes therein comprises depositing said glass layer, heating said glass layer to a flow temperature, etching said glass with a wet and dry process to form said contact holes, again heating said glass layer to a reflow temperature,

(b) forming said first layer of conductive lines comprises depositing a conductive layer on said glass layer, etching said conductive layer to form said conductive lines, and wet and dry etching said conductive lines for curving the edges of said lines,

(c) forming said intermetal layer comprises depositing an insulative material layer over said conductive lines, etching back said insulative material layer by 60-95%, and redepositing said insulative material to a thickness in a range from 6000 Å

to 14000 Å

, and

(d) forming said via holes in said intermetal layer comprises wet and dry etching said intermetal layer to form said via holes.

15. The process of claim 12 wherein said second gate layer is formed of polysilicon.

16. The process of claim 12 wherein said second gate layer is formed of a polysilicon and silicide sandwich for high speed operation.

17. The process of claim 12 wherein forming said N-channel stops and field oxide comprises,

thermally growing a thin silicon dioxide layer with a thickness in the range from 250 Å

to 100 Å

on said substrate depositing a silicon nitride layer with a thickness in the range from 1000 Å

to 2500 Å

on said silicon dioxide layer, thickness ratio of silicon nitride to silicon dioxide being in the range from 1;

1 to 7;

1,

removing said silicon nitride from all areas of said wafer except said device areas,

implanting boron ions into said substrate around N-channel device areas and around said N-well, the implantation energy being in the range form 25 keV to 50 keV, and

driving in said boron ions and thermally growing oxide in all areas except said device areas covered by said nitride, and

removing said nitride layer and said thin silicon dioxide layer.

18. The process of claim 12 wherein said first gate oxide layer has a thickness in a range from 250 Å

to 75 Å

.