Fiso sampling system

• US 4,833,445 A
• Filed: 06/07/1985
• Issued: 05/23/1989
• Est. Priority Date: 06/07/1985
• Status: Expired due to Fees

• Current Assignee: Sequence Limited (Skipton Building Society)
• Original Assignee: Sequence Limited (Skipton Building Society)
• Inventors: Buchele, William N.
• Primary Examiner(s): Sloyan, T. J.
• Application Number:
  US06/742,175
• Time in Patent Office: 1,446 Days
• Field of Search: 340/347 SH, 340/347 C, 340/347 CL, 340/347 M, 328/151, 358/138, 364/178, 364/179, 307/106
• US Class Current: 341/118
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence

Abstract

A fast-in, slow-out sampling system that operates at a very high sampling frequency at high accuracy. The system includes a parallel processing sampling structure controlled by a precision pulse generation system.

Claims

1. A high-speed sampling system comprising:

a transmission line for transmitting a signal;

means for coupling an input signal to said transmission line;

a plurality of sampling gates coupled, respectively, to like plurality substantially equispaced points on said transmission line with each of said sampling gates adapted to receive an enabling pulse;

a like plurality of storage means coupled to corresponding sampling gates, with each sampling gate for transferring the amplitude of the input signal at the point on said transmission line coupled to the sampling gate to the storage means coupled to the sampling gate when the sampling gate receives an enabling pulse;

means for generating an ordered like plurality of equispaced timing signals with each timing signal associated with a given one of said sampling gates;

means for generating an ordered like plurality of phase signals with each one of said phase signals associated with a given one of said timing signals and displaced from its associated signal by an adjustable phase delay interval;

adaptive means to adjust the displacement of each of said phase signals from its associated timing signal to compensate for propagation delay and for non-controllable hardware and temperature induced delays; and

a like plurality of enabling pulse generators, each enabling pulse generator coupled to a corresponding one of said sampling gates, adapted to receive the timing signal and phase signal associated with the corresponding sampling gate, and including a pair of step recovery diodes, characterized by a transition time between a high-impedance state and a low-impedance state of about 75 picoseconds, with each step recovery diode having a first terminal coupled to a common node, with each enabling pulse generator for generating an enabling pulse displaced from the timing signal associated with the corresponding sampling gate by the adjustable phase delay defined by the displacement between the timing signal and phase signal associated with the corresponding sampling gate with the rise time of the leading edge and fall time of the trailing edge of said enabling pulse being about 75 picoseconds to provide the precise timing required to sample signals at Gigahertz sampling rates.

2. The invention of claim 1 wherein said adaptive means comprises:

a test signal generator for generating a periodic signal with the period of the signal substantially equal to the time interval between adjacent timing signals;

means for coupling said test signal to said transmission line; and

means for adjusting the value of each phase signal so that the amplitude of the test transferred to each storage means is less than some predetermined value.

3. The invention of claim 2 wherein said timing signal generating means comprises:

a clock signal generator for generating a clock signal at a selected clock frequency and given clock period; and

a delay line, having a like plurality of outputs and adapted to receive said clock signal, for delaying said clock signal between successive outputs by a selected fraction of said clock period, with the delayed clock signals at said delay outputs being said ordered set of timing signals.

4. A high-frequency sampling system comprising:

a transmission line, with terminal impedance matched to the characteristic impedance of the transmission line, for receiving an input signal at an input terminal;

N sampling terminals coupled to said transmission line, with said N terminals being substantially equally distributed along said transmission line and separated by a distance D, with said N terminals being sequentially numbered from 1 to N, and with the first sampling terminal being nearest to the input terminal of the transmission line;

N sampling gates, with said N gates being sequentially numbered from 1 to N for identification and with each sampling gate coupled to the sampling terminal identified by the same number, said sampling gates for sampling the input signal when activated by a sampling pulse;

N sampling gate output buffers, with said N buffers numbered from 1 to N for identification and with each buffer coupled to the sampling gate identified by the same number, said buffers for holding the value of sampled input signal for the period between sampling pulses and for providing an output signal at a buffer output port, with magnitude of the output signal substantially equal to the magnitude of the sampled input signal;

a system clock for generating a clock input signal, Q, having frequency f_C and period T_C ;

N sampling gate drivers, with said N drivers being sequentially numbered from 1 to N for identification, and with each driver coupled to the sampling gate identified by the same number, with said drivers for receiving said clock input signal and a phase control signal and for generating said sampling pulse at time t_S, where t_S =t_I +t_P, where t_I is the time that the clock input signal is received at the ith driver, and t_P is a variable phase delay having a magnitude determined by the phase control signal;

clock signal delay means for delaying the receipt of the clock input signal at the kth driver, k=1 to N, by (k-1)t_D is a fixed time delay equal to T_C /N, with said clock signal delay means for clocking the sampling gates to achieve an overall sampling rate of Nf_C ;

means for generating N phase control signals, said N phase control signals numbered from 1 to N for identification, and for directing the mth control signal to the mth driver, m=1 to N, and for controlling the magnitude of each phase control signal to vary the magnitude of t_P in each driver to compensate for input signal propagation delay and variations in the dynamic characteristics of the sampling gates; and

N DEMUXs, with said N DEMUXs numbered from 1 to N for identification, and with the input of each DEMUX coupled to the output of a buffer identified by the same number, each DEMUX having N outputs for outputting N succeeding buffer outputs occurring over a time period of NT_C and with the output data rate of said DEMUXs equal to 1/N f_C.

5. The invention of claim 4 further comprising:

an analog memory array having inputs coupled to the outputs of said DEMUXs and having an analog output terminal.

6. The invention of claim 4 further comprising:

a high speed analog to digital converter coupled to each of said DEMUX outputs;

means for multiplexing the digital outputs of the analog to the digital converters to provide a continuous digital output data stream.

7. The invention of claim 5 or 6 wherein each of said drivers comprises:

a precision SRD pulse generation system for generating and positioning a high precision, controlled sub-nanosecond sample pulse.

8. The invention of claim 4 wherein said means for generating said phase control signals comprises:

means for providing a test signal at said input terminal, with the frequency of said test signal equal to (N/L)f_C where, if N is an even integer, L is any N odd integer, or, if N is an odd integer, L is any even integer;

means for sampling the test output data generated from sampling the test signal; and

means for adjusting the magnitude of the phase control signal based on the value of the sampled output data to adjust the magnitude of the test output data to predetermined values.

9. The invention of claim 4 further including a gain variation and DC offset correction loop comprising:

means for providing a test signal for determining each parallel element'"'"'s offsets,

means for providing a test signal for determining each parallel element'"'"'s gain,

means for utilizing the resulting store of offsets and gains to manipulate the real time output provided by the high-frequency sampling system to correct for gain variations and offsets.

10. The invention of claim 5 further comprising:

a hardware offset error correction means which substracts system offset errors from stored analog data as it is read out of memory arrays.

11. The invention of claim 4 wherein the width of said sampling pulse is t_PW, and wherein the length of said transmission line and values of said terminal impedance causes transient impulses associated with said sampling gates to be attenuated by a selected factor within time t_PW.

12. The invention of claim 11 further comprising:

a plurality of MUX circuits coupled to the outputs of said memory array.