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Signature analysis technique for defect characterization of CMOS static RAM cell failures

  • US 4,835,458 A
  • Filed: 11/09/1987
  • Issued: 05/30/1989
  • Est. Priority Date: 11/09/1987
  • Status: Expired due to Term
First Claim
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1. A method of determining a cause of a failure in a Complementary Metal-Oxide-Semiconductor (CMOS) Static Random Access Memory (SRAM) device comprised of a plurality of memory cells, each memory cell havinga first pair of CMOS transistors comprise of a first n-channel transistor and a first p-channel transistor coupled in series between a supply voltage (Vcc), and a return voltage (VSS), a second pair of CMOS transistors comprise of a second n-channel transistor and a second p-channel transistor coupled in series between the Vcc and VSS, such that a first node is formed at a junction of said first n-channel transistor and said first channel p-channel transistor, and said second node is formed at a junction of a second n-channel transistor and said second p-channel transistor, wherein gates of said first pair of CMOS transistors are coupled to said second nodes, and wherein gates of said second pair of CMOS transistors are coupled to said first node, comprising the steps of:

  • (a) isolating a defective memory cell within said memory;

    (b) making non-conductive said pair of p-channel transistors by applying a predetermined positive voltage on said p-channel transistors;

    (c) applying a first variable voltage on said first node while holding a first fixed voltage on said second node, wherein said first variable voltage varies between 0 V and a first predetermined positive voltage level;

    (d) measuring current at said two nodes as said first variable voltage is varied;

    (e) applying a second variable voltage on said second node while holding a second fixed voltage on said first node, wherein said second variable voltage varies between 0 V and a second predetermined positive voltage level;

    (f) measuring current at said two nodes as said second variable voltage is varied;

    (g) comparing results of voltage versus current for each of said n-channel transistors to known results of properly functioning n-channel transistors of an operative memory cell to determine of said failure is caused by one of said n-channel transistors.

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