Signature analysis technique for defect characterization of CMOS static RAM cell failures

• US 4,835,458 A
• Filed: 11/09/1987
• Issued: 05/30/1989
• Est. Priority Date: 11/09/1987
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Sang U.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/118,256
• Time in Patent Office: 568 Days
• Field of Search: 324/73 R, 324/73 AT, 324/158 R, 324/158 T, 371/20, 371/25, 371/26, 365/201, 365/154, 437/8
• US Class Current: 324/73.1
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/275 for testing individual semiconductor components within integrated circuits
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

An error testing process for the testing of CMOS static RAM memories. Individual static RAM memory cells that have failed are isolated. A typical cell has six transistors, two access, two n-channel and two p-channel. The access transistors are allowed to float which effectively isolates the cell. By application of voltages to the n-channel or p-channel transistors one set can be turned off and the remaining two n-channel or p-channel transistors can be tested with microprobes varying voltages for the forward and reverse bias testing. The graphs of the current flow from these tests are compared using the signature analysis technique so that not only the exact transistor which failed can be identified but the failure mechanism can also be identified. This process permits error testing without damage to the RAM memory and without physical isolation of the SRAM memory.

Claims

1. A method of determining a cause of a failure in a Complementary Metal-Oxide-Semiconductor (CMOS) Static Random Access Memory (SRAM) device comprised of a plurality of memory cells, each memory cell having

a first pair of CMOS transistors comprise of a first n-channel transistor and a first p-channel transistor coupled in series between a supply voltage (V_cc), and a return voltage (V_SS), a second pair of CMOS transistors comprise of a second n-channel transistor and a second p-channel transistor coupled in series between the V_cc and V_SS, such that a first node is formed at a junction of said first n-channel transistor and said first channel p-channel transistor, and said second node is formed at a junction of a second n-channel transistor and said second p-channel transistor, wherein gates of said first pair of CMOS transistors are coupled to said second nodes, and wherein gates of said second pair of CMOS transistors are coupled to said first node, comprising the steps of:

(a) isolating a defective memory cell within said memory;

(b) making non-conductive said pair of p-channel transistors by applying a predetermined positive voltage on said p-channel transistors;

(c) applying a first variable voltage on said first node while holding a first fixed voltage on said second node, wherein said first variable voltage varies between 0 V and a first predetermined positive voltage level;

(d) measuring current at said two nodes as said first variable voltage is varied;

(e) applying a second variable voltage on said second node while holding a second fixed voltage on said first node, wherein said second variable voltage varies between 0 V and a second predetermined positive voltage level;

(f) measuring current at said two nodes as said second variable voltage is varied;

(g) comparing results of voltage versus current for each of said n-channel transistors to known results of properly functioning n-channel transistors of an operative memory cell to determine of said failure is caused by one of said n-channel transistors.

2. The method described in claim 1 wherein step (c) further includes the step of:

applying said first variable voltage on said first node n-channel transistors in a negative bias direction from 0 V to a predetermined voltage while holding said first fixed voltage on said second node, wherein said first variable voltage varies between 0 V and a first predetermined negative voltage level and,

wherein step (e) further includes the step of;

applying said second variable voltage on said second node while holding said second fixed voltage on said first node, wherein said second variable voltage varies between 0 V and a second predetermined negative voltage level.

3. The method described in claim 1 further including the step of using said measuring steps to determine subthreshold leakage current, threshold voltage, transconductance, drain junction leakage, surface states induced leakage, gate leakage and drain current of a failed transistor.

4. The method described in claim 1 wherein said first and second variable voltages used range from approximately 0 V to 1 V in a positive direction and approximately 0 V to -1 V in a negative direction.

5. A method of determining a cause of a failure in a Complementary Metal-Oxide-Semiconductor (CMOS) Static Random Access Memory (SRAM) device comprised of a plurality of memory cells, each memory cell having a first pair of CMOS transistors comprise of a first n-channel transistor and a first p-channel transistor coupled in series between a supply voltage (V_cc), and a return voltage (V_ss), a second pair of CMOS transistors comprise of a second n-channel transistor and a second p-channel transistor coupled in series between the V_cc and V_ss such that a first node is formed at a junction of said first n-channel transistor and said first p-channel transistor, and said second node is formed at a junction of a second n-channel transistor and said p-channel transistor, wherein gates of said first pair of CMOS transistors are coupled to said second nodes, and wherein gates of said second pair of CMOS transistors are coupled to said first node, comprising the steps of:

(a) isolating a defective memory cell within said memory;

(b) making non-conductive said pair of n-channel transistors by applying a predetermined negative voltage on said n-channel transistors;

(c) applying a first variable voltage on said first node while holding a first fixed voltage on said second node, wherein said first variable voltage varies between 0 V and a first predetermined negative voltage level;

(d) measuring current at said two nodes as said first variable voltage is varied;

(e) applying a second variable voltage on said second node while holding a second fixed voltage on said first node, wherein said second variable voltage varies between 0 V and a second predetermined negative voltage level;

(f) measuring current at said two nodes as said second variable voltage is varied;

(g) comparing results of voltage versus current for each of said p-channel transistors to known results of properly functioning p-channel transistors of an operative memory cell to determine if said failure is caused by one of said p-channel transistors.

6. The method described in claim 5, wherein (c) further the step (c) further includes the step of:

applying said first variable voltage on said first node while holding said first fixed voltage on said second node, wherein said first variable voltage is varied between 0 V and a first predetermined positive voltage level; and

wherein step (e) further includes the step of;

applying said second variable voltage on said second node while holding said second fixed voltage on said first node, wherein said second variable voltage varies between 0 V and a second predetermined positive voltage level.

7. The method described in claim 5 further including the step of using said measuring steps to determine subthreshold leakage current, threshold voltage, transconductance, drain junction leakage, surface states induced leakage, gate leakage and drain current of a failed transistor.

8. The method described in claim 5, wherein said first and second variable voltages used range from approximately 0 V to 1 V in a positive direction and approximately 0 V to -1 V in a negative direction.

9. A method of determining a cause of a failure in a CMOS Static Random Access Memory (SRAM) comprised of a plurality of memory cells, each memory cell having a first transistor and a second transistor coupled in series between a power source terminal and a return terminal where said first transistor is a p-channel transistor and said second transistor is a n-channel transistor, a third transistor and a fourth transistor coupled in series between said power source terminal and said return terminal where said third transistor is a p-channel transistor and said fourth transistor is a n-channel transistor, a fifth transistor having a first terminal coupled to a junction of said first transistor and said second transistor and to gates of said third transistor and said fourth transistor, a sixth transistor having a first terminal coupled to junctions of said third transistor and said fourth transistor and to gates of said first transistor and said second transistor, said method comprising the steps of:

(a) isolating a defective memory cell within said memory by causing second terminals of said fifth transistor and said sixth transistor to float;

(b) making non-conductive said first transistor and said third transistor by applying a positive voltage of approximately 1 V on said power source terminal;

(c) applying a first variable voltage to said first terminal of said fifth transistor in a positive direction from approximately 0 V to 1 V while holding a first fixed voltage at approximately 1 V on said first terminal of said sixth transistor;

(d) measuring current at said first terminal of said fifth transistor;

(e) applying a second variable voltage to said first terminal of said sixth transistor in a positive direction from approximately 0 V to 1 V while holding a second fixed voltage at approximately 1 V on said first terminal of said fifth transistor;

(f) measuring current provided to said first terminal of said sixth transistor;

(g) comparing results of voltage versus current for each of said second and fourth transistors to known results of properly functioning transistors of an operative memory device to determine if said failure is caused by one of said second and fourth transistors.

10. The method described in claim 9 further including the steps of:

applying said first variable voltage on said first terminal of said fifth transistor in a negative direction from approximately 0 V to 1 V while holding said first fixed voltage at approximately 1 V on said first terminal of said sixth transistor;

applying said second variable voltage on said first terminal of said sixth transistor in a negative direction from approximately 0 V to -1 V while holding said second fixed voltage at approximately 1 V on said first terminal of said fifth transistor.

11. The method described in claim 9 further including the step of using said measuring steps to determine subthreshold leakage current, threshold voltage, transconductance, drain junction leakage, surface states induced leakage, gate leakage and drain current of a failed transistor.

12. A method of determining a cause of a failure in a CMOS Static Random Access Memory (SRAM) comprised of a plurality of memory cells;

each memory cell having a first transistor and a second transistor coupled in a series between a power source terminal and a return terminal where said first transistor is a p-channel transistor and said second transistor is a n-channel transistor, a third transistor and a fourth transistor coupled in a series between said power source terminal and said return terminal where said third transistor is a p-channel transistor and said fourth transistor is a n-channel transistor, a fifth transistor having a first terminal coupled to junctions of said first transistor and said second transistor and to gates of said third transistor and said fourth transistor, a sixth transistor having a first terminal coupled to junctions of said third transistor and said fourth transistor and to gates of said first transistor and said second transistor;

said method of comprising the steps of;

(a) isolating a defective memory cell within said memory by causing second terminals of said fifth transistor and said sixth transistor to float;

(b) making non-conductive said second transistor and said fourth transistor by applying a negative voltage of approximately -1 V on said return terminal;

(c) applying a first variable voltage to said first terminal of said fifth transistor in a negative direction from approximately 0 V to 1 V while holding a first fixed voltage at approximately 1 V on said first terminal of said sixth transistor;

(d) measuring current provided to said first terminal of said fifth transistor;

(e) applying a second variable voltage to said first terminal of said sixth transistor in a negative direction from approximately 0 V to -1 V while holding a second fixed voltage at approximately -1 V on said first terminal of said fifth transistor;

(f) measuring current provided to said first terminal of said sixth transistor;

(g) comparing results of voltage versus current for each of said first and third transistors to known results of properly functioning transistors of an operative memory device to determine if said failure is caused by one of said first and third transistors.

13. The method described in claim 12 further including the steps of:

applying said first variable voltage on said first terminal of said fifth transistor in a positive direction from approximately 0 V to -1 V while holding said first fixed voltage at approximately 1 V on said first terminal of said sixth transistor;

applying said second variable voltage on said first terminal of said sixth transistor in a positive direction from approximately 0 V to 1 V while holding voltage at approximately -1 V on said first terminal of said fifth transistor.

14. The method described in claim 12 further including the step of using said measuring steps to determine subthreshold leakage current, threshold voltage, transconductance, drain junction leakage, surface states induced leakage, gate leakage and drain current of a failed transistor.