Isolation amplifier with precise timing of signals coupled across isolation barrier

• US 4,835,486 A
• Filed: 05/10/1988
• Issued: 05/30/1989
• Est. Priority Date: 04/28/1986
• Status: Expired due to Term

• Current Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Original Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Inventors: Somerville, Thomas A.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/192,219
• Time in Patent Office: 385 Days
• Field of Search: 330/10, 330/207 A, 330/251, 307/357, 307/360, 328/127
• US Class Current: 330/10
• CPC Class Codes: H03F 3/38 DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers switched capacitor amplifiers H03F3/005
• CPC Class Codes: H03G 11/002 without controlling loop H03G11/004, H03G11/006, H03G11/008, H03G11/02, H03G11/04, H03G11/06, H03G11/08 take precedence
• CPC Class Codes: H03H 11/1213 using transistor amplifiers H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/126 using a single operational amplifier H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence

Abstract

A low cost, high frequency isolation amplifier includes a first voltage-to-frequency converter producing a first pair of complementary pulses in response to an analog input signal and applying them to a pair of low capacitance capacitors constituting the isolation barrier. The isolation barrier differentiates edges of the first pair of pulse signals and applies the resulting signals to inputs of a sense amplifier including a differential amplifier, a pair of comparators, and a flip-flop to precisely reconstruct the first pair of complementary pulse signals, which then are fed into a decoder circuit including a phase locked loop. The phase locked loop includes a phase detector receiving the reconstructed pair of complementary pulse signals and a second pair of complementary pulse signals produced by a second voltage-to-frequency converter. The output of the phase detector is integrated by a filter circuit, the output of which produces a voltage that represents the analog input signal and causes the output of the second voltage-to-frequency converter to be synchronized with the second pair of complementary pulse signals when the analog output signal matches the analog input signal.

Claims

1. A digital isolation circuit comprising in combination:

(a) first means for producing a first pulse signal and a second pulse signal that is the logical complement of the first pulse signal;

(b) first and second isolation barrier means for coupling a portion of each of the first and second pulse signals, respectively, from the first means to a first terminal and a second terminal;

(c) means for differentiating the first and second pulse signals as they are coupled across the first and second isolation barrier means, respectively, to produce differentiated third and fourth pulse signals each having certain edges with times of occurrence corresponding precisely to times of occurrence of the certain edges of the first pulse signal;

(d) means for amplifying the third and fourth pulse signals to produce a differential signal;

(e) first and second comparators; and

(f) means for applying the differential signal to inputs of the first and second comparators to cause the first and second comparators to sense relative positive and negative excursions of the differential signal, and thereby cause the first and second comparators to switch at times precisely corresponding to times of occurrence of leading and trailing edges, respectively, of the first pulse signal.

2. The digital isolation circuit of claim 1 wherein the differentiating means includes first and second input impendences, the first input impedance being matched to the second input impedence, and wherein the first and second isolation barrier means have equal impedances, whereby high frequency common mode rejection is improved.

3. The digital isolation circuit of claim 2 wherein the first and second isolation barrier means include first and second capacitors, the first capacitor being connected between the first terminal and a third terminal, the second capacitor being connected between the second terminal and a fourth terminal, the first and second impedances including first and second resistors, respectively, the differentiating means including the first and second isolation barrier means and the first and second resistors, the first resistor being connected between the first terminal and a reference voltage conductor, the second resistor being connected between the second terminal and a reference voltage conductor.

4. The digital isolation circuit of claim 3 wherein the first and second comparators each have a reference input connected to relatively positive and negative reference threshold voltages, respectively, the digital isolation circuit including a differential amplifier having a pair of inputs connected, respectively, to the first and second terminals and an output connected to another input of each of the first and second comparators, and means for producing an output pulse signal and including a flip-flop having input connected to outputs of the first and second comparators, one output of the flip-flop producing the output pulse signal.

5. The digital isolation circuit of claim 3 wherein the first and second capacitors each have a capacitance of less than approximately 3 picofarads.

6. The digital isolation circuit of claim 5 wherein the first and second capacitors are fringe capacitors.

7. The digital isolation circuit of claim 6 wherein a breakdown voltage of the first and second capacitors exceeds 1500 volts.

8. The digital isolation circuit of claim 2 wherein the differentiating means produces voltage spikes on the first and second terminals, which voltage spikes are very short compared to the interval between successive pulses of the first and fourth pulse signals.

9. The digital isolation circuit of claim 8 wherein the spikes of the first and fourth pulse signals decay to a zero reference level substantially by the occurrence of the next edge of either said first pulse signal or said four signal, whereby the same relative level of each spike is sensed by the first and second comparators, thereby causing the first and second comparators to switch at times corresponding precisely to the times of occurrence of the certain edges of the first pulse signal.

10. A method of operating a digital isolation circuit comprising the steps of:

(a) producing a first pulse signal and a second pulse signal that is the logical complement of the first pulse signal;

(b) coupling a portion of each of the first and second pulse signals across an isolation barrier;

(c) differentiating the first and second pulse signals as they are coupled across the isolation barrier to produce differentiated third and fourth pulse signals each having certain edges corresponding precisely to times of occurrence of the certain edges of the first pulse signal;

(d) amplifying the third and fourth pulse signals to produce a differential signal; and

(e) applying the differential signal to inputs of first and second comparators that sense relative positive and negative excursions of the differential signal, causing the first and second comparators to switch at times precisely corresponding to the leading and trailing edges of the first pulse signal.