MOS voltage to current converter
First Claim
1. A MOS circuit comprising:
- a first supply voltage terminal for receiving a first supply voltage;
a second supply voltage terminal for receiving a second supply voltage;
a third supply voltage terminal for receiving a conversion voltage;
an output current sink terminal;
an output current source terminal;
voltage divider means coupled between said second and third supply voltage terminals, wherein the conversion voltage provides power for said circuit and may vary over a range extending from two thresholds voltage above the second supply voltage to a Vbe above the first supply voltage, said voltage divider means having a voltage reference node for providing a reference voltage relative to the conversion voltage;
linear reference current generator means coupled to said first, second, and third supply voltage terminals, and coupled to said voltage reference node for providing a linear reference current whose magnitude varies linearly in response to a corresponding change in the conversion voltage; and
output means coupled between said second and third supply voltage terminals and coupled to said linear reference current generator means for providing an output sink current and an output source current at said output current sink terminal and said output current source terminal, respectively, wherein the magnitude of the output sink current and the magnitude of the output source current are a ratio of the magnitude of the linear reference current.
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Accused Products
Abstract
A voltage to current converter circuit manufactured with a MOS process generates a linear reference current over a wide bandwidth and operates with an input signal that varies to either supply rail. A voltage divider network scales an input voltage for conversion to a linear current by a cascode current mirror and a gain resistor. The value of the gain resistor determines the transconductance of the conversion from voltage to current. A second current mirror provides feedback to keep the reference current accurate. An output stage makes available high impedance source and sink current output terminals wherein a source current and a sink current relative to the reference current are provided. Several voltage to current converter circuits may be coupled together to provide a addition, subtraction, multiplication, and other circuit and system functions.
20 Citations
16 Claims
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1. A MOS circuit comprising:
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a first supply voltage terminal for receiving a first supply voltage; a second supply voltage terminal for receiving a second supply voltage; a third supply voltage terminal for receiving a conversion voltage; an output current sink terminal; an output current source terminal; voltage divider means coupled between said second and third supply voltage terminals, wherein the conversion voltage provides power for said circuit and may vary over a range extending from two thresholds voltage above the second supply voltage to a Vbe above the first supply voltage, said voltage divider means having a voltage reference node for providing a reference voltage relative to the conversion voltage; linear reference current generator means coupled to said first, second, and third supply voltage terminals, and coupled to said voltage reference node for providing a linear reference current whose magnitude varies linearly in response to a corresponding change in the conversion voltage; and output means coupled between said second and third supply voltage terminals and coupled to said linear reference current generator means for providing an output sink current and an output source current at said output current sink terminal and said output current source terminal, respectively, wherein the magnitude of the output sink current and the magnitude of the output source current are a ratio of the magnitude of the linear reference current. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit comprising:
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a first supply voltage terminal; a second supply voltage terminal; a third supply voltage terminal; an output current sink terminal; an output current source terminal; a gain terminal; a first resistor coupled between said third supply voltage terminal and a voltage reference node; a second resistor coupled between the voltage reference node and said second supply voltage terminal; a first field effect transistor having a source coupled to said first supply voltage terminal, and having a gate and a drain; a second field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to a current reference node, and having a drain; a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and having a drain; a fourth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor, and having a drain; a sixth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to said output current source terminal; a seventh field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said third supply voltage terminal, and a gate and a drain coupled to the current reference node; a ninth field effect transistor having a source and a gate coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; a tenth field effect transistor having a drain coupled to the current reference node, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said second supply voltage terminal; a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said second supply voltage terminal; a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said second supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said second supply voltage terminal.
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9. A MOS circuit comprising:
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a first supply voltage terminal for receiving a first supply voltage; a second supply voltage terminal for receiving a second supply voltage; a third supply voltage terminal for receiving a conversion voltage; an output current sink terminal; an output current source terminal; voltage divider means coupled between said first and third supply voltage terminals, wherein the conversion voltage provides power for said circuit and may vary over a range extending from two threshold voltages below the first supply voltage to a Vbe below the second supply voltage, said voltage divider means having a voltage reference node for providing a reference voltage relative to a conversion voltage; linear reference current generator means coupled to said first, second, and third supply voltage terminals, and coupled to said voltage reference node for providing a linear reference current whose magnitude varies linearly in response to a corresponding change in the conversion voltage; and output means coupled between said first and third supply voltage terminals and coupled to said linear reference current generator means for providing an output sink current and an output source current at said output current sink terminal and said output current source terminal, respectively, wherein the magnitude of the output sink current and the magnitude of the output source current are a ratio of the magnitude of the linear reference current. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A circuit comprising:
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a first supply voltage terminal; a second supply voltage terminal; a third supply voltage terminal; an output current sink terminal; an output current source terminal; a gain terminal; a first resistor coupled between said first supply voltage terminal and a voltage reference node; a second resistor coupled between the voltage reference node and said third supply voltage terminal; a first field effect transistor having a source coupled to said first supply voltage terminal, and having a gate and a drain; a second field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to a current reference node, and having a drain; a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and having a drain; a fourth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor, and having a drain; a sixth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to said output current source terminal; a seventh field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said first supply voltage terminal, and a gate and a drain coupled to the current reference node; a ninth field effect transistor having a source and a gate coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; a tenth field effect transistor having a drain coupled to the current reference node, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said third supply voltage terminal; a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said third supply voltage terminal; a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said third supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said third supply voltage terminal.
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Specification