Trench transistor

• US 4,835,584 A
• Filed: 03/16/1987
• Issued: 05/30/1989
• Est. Priority Date: 11/27/1986
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Lancaster, Loren T.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): PRENTY, MARK V
• Application Number:
  US07/027,992
• Time in Patent Office: 806 Days
• Field of Search: 357/55, 357/23.1, 357/23.6, 357/59
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

The specification describes a new MOS transistor structure in which the source gate and drain are formed within a trench in the semiconductor substrate. The gate width is determined by the depth of the trench and can be increased substantially without increasing the surface area occupied by the transistor. The result is a transistor with exceptionally high gain for a given surface area. Forming the transistor within and over a series of trenches further enhances this effect.

Claims

1. MOS transistor device comprising:

a semiconductor substrate,

a trench formed into said semiconductor substrate said trench comprising a first pair of oppositely disposed sidewalls, a second pair of oppositely disposed sidewalls, and a bottom,

an MOS transistor source region extending vertically entirely along one of said first pair of sidewalls and a portion of said bottom,

an MOS transistor drain region extending vertically entirely along the other of said first pair of sidewalls and a portion of said bottom,

a gate dielectric layer covering said second pair of sidewalls and extending across said bottom,

and an MOS transistor gate electrode extending along said second pair of sidewalls and extending across said bottom and having a pair of edges parallel to said first pair of sidewalls and within said trench, one edge of said pair of edges of said gate electrode overlying the edge of said source region in a portion of said bottom and the other edge of said pair of edges of said gate electrode overlying the edge of the drain region in a portion of said bottom, said source and drain regions extending along said second pair of sidewalls to said gate electrode.

2. Device of claim 1 in which the semiconductor is silicon.

3. Device of claim 1 in which the gate electrode is polysilicon.

4. Device of claim 1 further including an additional transistor device as defined in claim 1 adjacent to the first with the gate electrode of the first transistor and the gate electrode of the additional transistor merged together.

5. MOS transistor device comprising:

a plurality of trenches formed side by side into the surface of a semiconductor substrate, said trenches comprising bottoms and first and second pairs of sidewalls,

an MOS gate electrode structure formed continuously over the said trenches and into said trenches so as to bisect at least a pair of said trenches,

a first impurity region formed in the substrate along one side of said gate electrode structure including the portion of the substrate extending along one sidewall of the first pair of sidewalls of the said at least a pair of trenches, said impurity region forming the source of the MOS transistor,

and a second impurity region formed in the substrate along the opposite side of said gate electrode structure including the portion of the substrate extending along the opposite sidewall of the first pair of sidewalls of the said at least a pair of trenches, said second impurity region forming the drain of the MOS transistor, said first and second regions extending to said bottoms of said trenches and to said gate electrode structure on said second pair of sidewalls and bottom.

6. Device of claim 5 in which the said trenches are filled with dielectric material, said dielectric material being deposited after said gate electrode.

7. Device of claim 5 in which said trenches are filled with dielectric material except for the region above the gate electrode, which region is filled with gate electrode material.