Adaptive lithography system to provide high density interconnect

• US 4,835,704 A
• Filed: 12/29/1986
• Issued: 05/30/1989
• Est. Priority Date: 12/29/1986
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Eichelberger, Charles W., Welles, Kenneth B. II, Wojnarowski, Robert J.
• Primary Examiner(s): Chin, Gary
• Assistant Examiner(s): Cosimano, Edward R.
• Application Number:
  US06/947,461
• Time in Patent Office: 883 Days
• Field of Search: 148/DIG. 93, 204/37.6, 346/762, 364/488, 364/489, 364/490, 364/491, 364/559, 437/16, 437/943
• US Class Current: 430/22
• CPC Class Codes: G03F 7/704 Scanned exposure beam, e.g. raster-, rotary- and vector scanning mask projection exposure involving relative movement of patterned beam and workpiece during imaging G03F7/70358
• CPC Class Codes: H01L 21/6715 Apparatus for applying a liquid, a resin, an ink or the like H01L21/67126 takes precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/75753 Means for optical alignment, e.g. sensors
• CPC Class Codes: H01L 2224/758 Means for moving parts
• CPC Class Codes: H01L 2224/759 Means for monitoring the connection process
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/76 Apparatus for connecting with build-up interconnects
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10S 148/093 : Laser beam treatment in general
• CPC Class Codes: Y10S 430/146 : Laser beam

Abstract

An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate. The procedure is performed in four basic steps: first an artwork representation for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging, the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate. Finally, the modified artwork representation is used to drive a direct writing laser lithography system that actually forms the high density interconnections of the integrated circuits on the substrate. The artwork representations are stored in computer data bases in vector form to minimize storage requirements. The laser beam produced by the lithography system is raster scanned on the substrate. Modulation of the laser beam is controlled by the real time conversion of the vector representation of the modified artwork to be a bit mapped representation. To assure accurate formations of the interconnects, a feedback alignment system is used to accurately position the laser beam throughout its raster scan.

Claims

1. An adaptive method of providing high density interconnections among a plurality of integrated circuits on a substrate, said method comprising the steps of:

generating an artwork representation for the interconnections among said integrated circuits at predetermined ideal positions and orientations on said substrate;

determining the actual position and orientation of each of said integrated circuits on said substrate;

modifying said artwork representation for said interconnections among said integrated circuits to properly interconnect at least two of said integrated circuits in their actual positions and orientations, wherein said at least two integrated circuits are not in their ideal positions and orientations; and

forming high density interconnections among said integrated circuits using said modified artwork representation.

2. The adaptive lithography system according to claim 1 wherein:

said integrated circuits are individual chips separate from said substrate and fixed to said substrate.

3. The method according to claim 1 wherein said predetermined ideal positions and orientations and the locations of connection pads on each integrated circuit are stored in a first data base and the step of generating an artwork representation comprises the steps of:

providing a printed circuit layout of metallized conducting paths from said positions, orientations and connection pad locations and a list of the required connections among said connection pads of said integrated circuits; and

storing a representation of said printed circuit layout in a second data base decribing an interconnection structure for providing said high density interconnections among said integrated circuits in their ideal positions and orientations.

4. The method according to claim 3 wherein the step of storing is performed by storing a vector representation of said printed circuit layout in said second data base.

5. The method according to claim 3 wherein the step of determining comprises the steps of:

aligning an image of each of said integrated circuits in an image field of said substrate;

comparing each of said images of said integrated circuits with said predetermined ideal positions and orientation of said each integrated circuit on said substrate; and

calculating an offset and rotation for each of said integrated circuits based on said comparing step.

6. The method according to claim 5 wherein:

said step of aligning includes the step of generating a third data base describing the actual locations of predetermined features of each of said integrated circuits with respect to said substrate and wherein said step of comparing compares entries in said first and third data bases.

7. The method accoding to claim 6 wherein said modifying step comprises the step of producing a fourth data base by altering said second data base according to said calculated offset and rotation for each of said integrated circuits to produce a fourth data base storing a vector representation of the modified artwork.

8. The method according to claim 7 wherein said forming step is comprises the steps of:

converting the vector representation of the modified artwork in said fourth data base to a bit mapped representation of said modified artwork; and

controlling a raster scanned laser beam in a metallized circuit forming system in accordance with said bit mapped representation of said modified artwork.

9. An adaptive lithography system for providing high density interconnections of integrated circuits on a substrate, said system comprising:

memory means for storing in a first data base an artwork representation for the interconnections among said integrated circuits at predetermined ideal positions and orientations on said substrate;

imaging means for determining the actual position and orientation of each of said integrated circuits on said substrate;

computing means responsive to said memory means and said imaging means for modifying said artwork representation to match the actual position and orientation of each of said integrated circuits and for storing a modified artwork representation as a second data base in said memory means; and

laser lithography means controlled by said modified artwork representation in said second data base for forming high density interconnections among said integrated circuits.

10. The adaptive lithography system according to claim 9 wherein:

said integrated circuits are individual chips separate from said substrate and fixed to said substrate.

11. The adaptive lithography system according to claim 9 wherein the representations in said first and second data bases are vector representations, said system further comprising conversion means for converting the vector representation in said second data base to a bit mapped representation used to control said laser lithography means.

12. The adaptive lithography system according to claim 11 wherein said laser lithography means comprises:

a direct writing laser producing a laser beam;

scanning means for scanning said laser beam in a raster on said substrate; and

modulating means responsive to said bit mapped representation for modulating said laster beam as it is raster scanned on said substrate so as to define said interconnections according to said modified artwork representation.

13. The adaptive lithography system according to claim 12 further comprising:

alignment means for accurately determining the position of said scanning means at all times during scanning; and

said computing means being responsive to said alignment means for controlling said scanning means to accurately position said laser beam at points as it is raster scanned on said substrate.

14. The adaptive lithography system according to claim 13 wherein said scanning means comprises:

deflecting means for deflecting said laser beam in a first direction; and

displacement means carrying said substate for displacing said substrate in at least a second direction at an angle to said first direction; and

wherein said alignment means comprises;

an alignment laser, graticule and photodiode, said alignment laser producing a light beam deflected by said deflecting means the deflection of which is sensed by said graticule and photodiode; and

said computing means being responsive to said photodiode and said imaging means.