Interconnection area decision processor

• US 4,835,705 A
• Filed: 02/10/1987
• Issued: 05/30/1989
• Est. Priority Date: 02/17/1986
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Terai, Masayuki, Fujino, Yasuhiro, Noda, Tomoyoshi, Ajioka, Yoshihide
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/014,374
• Time in Patent Office: 840 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

The present invention provides an interconnection area decision processor for deciding vertical widths of areas employed for interconnection of a gate array. The interconnection area decision processor predicts which interconnection area each signal net passes on the basis of previously created data on cell arrangement and data on arrangement of transistor rows on a chip to estimate interconnection congestion per channel on the basis of the result of prediction and decide the number of transistor rows to be assigned to each channel on the basis of the estimated interconnection congestion, thereby to create data on the vertical width of each channel. Thus, density of integration can be improved by increasing the number of tracks of channels having large numbers of interconnections and decreasing the number of tracks of channels having small numbers of interconnections.

Claims

1. For a large scale integrated circuit formed with rows of transistors horizontally disposed between left and right sides of a chip and wherein said rows are arranged throughout the chip between the upper and lower ends thereof so that transistors on said chip which are to be employed as cells can be arbitrarily selected and other transistors can be used as interconnection areas:

a method of determining vertical widths of channels between said rows during interconnection processing of a particular circuit arrangement on the chip, comprising the steps of

storing first data defining a cell arrangement on the chip;

storing second data defining a transistor arrangement on the chip;

in response to said first and second data, predicting a loose interconnection path as to through which channel each signal net passes, wherein each said signal net is a set of cell terminals to be interconnected;

estimating interconnection congestion for each said channel on the basis of a thereby predicted loose interconnection path; and

determining a number of said transistor rows to be assigned to each said channel on the basis of thereby estimated interconnection congestion to create data on the vertical width of each said channel.

2. The method of claim 1, wherein said step of determining includes arithmetically processing said cell arrangement data and said channel vertical width data for generating interconnection data.

3. For a large scale integrated circuit formed with rows of transistors horizontally disposed between left and right sides of a chip and wherein said rows are arranged throughout the chip between the upper and lower ends thereof so that transistors on said chip which are to be employed as cells can be arbitrarily selected and other transistors can be used as interconnection areas:

an interconnection area decision processor for determining vertical widths of channels between said rows during interconnection processing of a particular circuit arrangement on the chip, comprising

first memory means for storing predetermined data defining a cell arrangement on the chip;

second memory means for storing data defining a transistor arrangement on the chip;

loose interconnection path decision means responsive to said data stored in said first and second memory means for predicting a loose interconnection path as to through which channel each signal net passes, wherein each said signal net is a set of cell terminals to be interconnected;

interconnection congestion estimating means for estimating interconnection congestion for each said channel on the basis of said loose interconnection path predicted by said loose interconnection path deciding means; and

interconnection area assigning means for determining a number of said transistor rows to be assigned to each said channel on the basis of said interconnection congestion estimated by said interconnection congestion estimating means, to create data on the vertical width of each said channel.

4. The processor of claim 3, including third memory means for storing said channel vertical width data.

5. The processor of claim 3, wherein said interconnection congestion estimating means includes means for predicting a schematic interconnection number per channel;

and said interconnection area assigning means includes means responsive to said schematic interconnection number for determining the number of transistor rows to be assigned to each said channel.

6. The processor of claim 3, including an interconnection processing computer responsive to said cell arrangement data stored in said first memory means and said channel vertical width data stored in said third memory means for generating interconnection data.

7. The processor of claim 6, including fourth memory means for storing said interconnection data.