Data acquisition system for capturing and storing clustered test data occurring before and after an event of interest

• US 4,835,736 A
• Filed: 08/25/1986
• Issued: 05/30/1989
• Est. Priority Date: 08/25/1986
• Status: Expired due to Term

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Easterday, John L.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Mohamed, Ayni
• Application Number:
  US06/899,854
• Time in Patent Office: 1,009 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/20
• US Class Current: 711/218
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware

Abstract

A memory pointer circuit includes a plurality of counters and a programmable logic array for controlling the counters to generate addresses for an acquisition memory. The programmable logic array directs a lower counter to generate a repeating sequence of addresses to store data before an event occurs, each pass through the sequence causing previously written data to be overwritten until an event has occurred and is stored in memory. The programmable logic array then directs the upper counters to increment and the lower counter to generate a following sequence of addresses to store data after the event occurs. Once the following sequence is complete, the upper counters are again incremented and the repeating sequence of addresses is again generated. The procedure is repeated to store multiple clusters of data and events in the acquisition memory. Once the acquisition memory is full, the stored data and events can be saved or overwritten.

Claims

1. In a data acquisition system, a memory pointer circuit for storing in an acquisition memory test data from a circuit under test occurring before and after specified events, the memory pointer circuit comprising:

signaling means for signaling the occurrence of each specified event;

address generating means in communication with the signaling means and the acquisition memory for generating memory addresses to store test data and specified events in memory; and

control means in communication with the signaling means and the address generating means for directing the address generating means to generate a repeating series of addresses to store test data in memory occurring before each specified event, the repeating series of addresses causing the stored test data to overwrite previously stored test data in memory until the specified event is signaled and stored in memory, the control means then directing the address generating means to generate a following series of addresses to store test data occurring after each specified event is stored,

the control means directing the address generating means to generate a second repeating series of addresses before and a second following series of addresses after a second specified event is sensed to enable the memory to store a plurality of specified events along with related test data.

2. The circuit of claim 1 in which the address generating means includes a plurality of digital counters, a first counter for generating a repeating sequence of lower order address bits and a second counter for generating higher order address bits, the second counter incrementing after the occurrence of a specified event and incrementing again after completion of the following series of addresses to generate a plurality of repeating and following series of addresses for memory.

3. The circuit of claim 1 in which the control means includes a programmable logic array means for generating control signals in response to a specified event to control the address generating means.

4. The circuit of claim 1 including RAM memory means for determining when the acquisition memory is full and alerting the control means that further storage of data will overwrite previously stored events and related data.

5. In a data acquisition system, a memory pointer circuit for storing in an acquisition memory test data from a circuit under test occurring before and after specified events, the memory pointer circuit comprising:

an event bus for signaling the occurrence of a specified event;

a first counter for generating the lower portion of the memory address;

second counter means for generating the upper portion of the memory address; and

a programmable logic array means in communication with the event bus and the first and second counters for directing the first counter to generate a repeating series of address bits as the lower portion of the memory address to store test data in the acquisition memory occurring before the specified event, each generation of address bits in the series causing the memory to overwrite previously stored test data at that address until the specified event occurs and is stored in memory, the logic means then directing the second counter to increment the upper portion of the memory address and generate with the first counter a following series of addresses to store test data occurring after each specified event, the logic array means further directing the second counter to increment the upper portion of the memory address again after completion of the following series of addresses, the first counter then generating another repeating series of addresses as the lower portion of the memory address and generating with the second counter another series of following addresses for each specified event that is stored.

6. The memory pointer circuit of claim 5 in which the first and second counter means comprise 4-bit digital counters.