Frasable electrically programmable read only memory cell using a three dimensional trench floating gate

• US 4,835,741 A
• Filed: 06/02/1986
• Issued: 05/30/1989
• Est. Priority Date: 06/02/1986
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Baglee, David A.
• Primary Examiner(s): Fears, Terrell W.
• Assistant Examiner(s): Koval, Melissa J.
• Application Number:
  US06/869,498
• Time in Patent Office: 1,093 Days
• Field of Search: 365/185, 365/182, 365/149, 357/23.6, 357/51, 357/23.5, 357/55
• US Class Current: 365/185.1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

An electrically programmable read only memory device formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate.

Claims

1. An electrically programmable read only memory device formed in a face of a semiconductor substrate, comprising a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in said substrate and including a tunnel device coupled to a source of said floating gate transistor and having a floating gate connected to the floating gate of said floating gate transistor and a control gate connected to the control gate of said floating gate transistor.

2. A device according to claim 1, wherein said substrate is silicon and said floating and control gates are polysilicon.

3. A device according to claim 2, including a selection transistor formed in said substrate in series with said floating gate transistor.

4. A device according to claim 2, wherein said substrate is P-type silicon, said and the thickness of said polysilicon gates are each about 0.4 microns.

5. A device according to claim 2, wherein said polysilicon layers are conformally deposited.

6. A device according to claim 1, wherein said trench has a substantially rectangular cross section which has a common moat region on at least two opposed ends thereof.

7. A device according to claim 6, wherein said trench has a width in the range of about 2 to 5 microns, a length of 2 to 5 microns and a depth of 1 to 3 microns.

8. A device according to claim 2, including a silicon dioxide region between said substrate and said floating gate having a thickness of 100 to 500 Angstroms.

9. A device according to claim 1, wherein said device is electrically erasable.