Vertical MOSFET with reduced bipolar effects

• US 4,837,606 A
• Filed: 02/12/1987
• Issued: 06/06/1989
• Est. Priority Date: 02/22/1984
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Goodman, Alvin M., Goodman, Lawrence A.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US07/014,196
• Time in Patent Office: 845 Days
• Field of Search: 357/23.3, 357/23.4, 357/23., 357/23.12, 357/86, 357/88, 357/89, 357/90
• US Class Current: 257/139
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.

Claims

1. In a vertical MOSFET device comprising a semiconductor wafer having first and second opposing major surfaces, a first conductivity type drain region at the first surface, a second conductivity type drain region at the extending from the first surface so as to form a PN junction with the drain region, a first conductivity type source region extending a predetermined depth into the body region so as to form a source/body PN junction, the spacing between the source/body PN junction and body/drain PN junction defining a channel region in the body region at the first surface, a source electrode contacting the source and body regions at the first surface, an insulated gate electrode overlying the channel region on the first surface, and a drain electrode on the second surface, the improvement comprising:

a second conductivity type supplementary region contiguous with the body region and having a high areal dopant concentration compared to that of the body region, the supplementary region including a region of peak dopant concentration that is substantially parallel to the first surface at a predetermined depth therefrom and extends laterally beneath at least a portion of the channel region.

2. A device in accordance with claim 1, wherein said supplementary region peak dopant concentration is at a depth which is substantially equal to or greater than said predetermined depth of said source/body PN junction.

3. A device in accordance with claim 1, wherein said drain region is disposed on a layer of similar conductivity type and said similar conductivity type layer is adjacent to said opposing wafer surface.

4. A device in accordance with claim 1, wherein said drain region is disposed on a layer of opposite conductivity type, said opposite conductivity type layer being adjacent to said opposing wafer surface.

5. In a vertical MOSFET device comprising a semiconductor wafer having first and second opposing major surfaces, a first conductivity type drain region at the first surface, a second conductivity type body region extending from the first surface so as to form a PN junction with the drain region, a first conductivity type source region extending a predetermined depth into the body region so as to form a source/body PN junction, the spacing between the source/body PN junction and body/drain PN junction defining a channel region in the body region at the first surface, a source electrode contacting the source and body regions at the first surface, an insulated gate electrode overlying the channel region on the first surface, and a drain electrode on the second surface, the improvement comprising:

a second conductivity type supplementary region contiguous with the body region and having a high areal dopant concentration compared to that of the body region, said supplementary region disposed substantially parallel to the first surface at a depth sufficient to substantially reduce punchthrough that occurs at the source/body PN junction and extending under at least a portion of the channel region to suppress the effect of the parasitic bipolar transistor formed by the source, body and drain regions.