Controlling asynchronously operating peripherals

• US 4,837,680 A
• Filed: 08/28/1987
• Issued: 06/06/1989
• Est. Priority Date: 08/28/1987
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pousson, Michael W. Jr., Norris, Richard E., Miller, Arnold G., Kern, Robert F., Wagner, Robert E., Crockett, Robert N.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US07/090,722
• Time in Patent Office: 648 Days
• Field of Search: 364/200, 364/309, 364/900
• US Class Current: 710/104
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor

Abstract

A plurality of host processors share access to a peripheral data storage subsystem and each have program means for controlling asynchronous operations of the subsystem. Control blocks in each of the host processors are addressably linked together for enabling inferred access to a unit control block (UCB) for any of a plurality of peripheral devices in the subsystem. The subsystem selectively groups some of the devices such that only devices designated as primary devices are addressably accessible by host processor application programs. Other devices in the respective groups are secondary devices and are accessed by the subsystem whenever the primary devices in the same group cannot perform a host processor commanded operation. Means are provided for identifying the secondary devices to all of the host processors.

Claims

1. In a method of operating a multiple host processor data processor system wherein a plurality of host processors are commonly connected to a peripheral subsystem having a programmed control unit and a plurality of attached peripheral devices, path address means in the subsystem for accessing the devices from the programmed control unit, each of the peripheral devices having means for performing host related data processing functions which are commanded by any one of the host processors, a fast access cache in the programmed control unit for storing data during data transfer operations between any of the commonly connected host processors and addressed ones of the devices, the host processors accessing data areas in the cache and in the peripheral devices via addresses of the devices, said addresses of the devices including said addresses with paths not being individually and separately addressable by the host processors, each of the commonly connected host processors having a unit control block for and describing the peripheral devices and control tables describing current configuration and status of the peripheral subsystem;

the steps of;

grouping less than all of said peripheral devices into one or more logical groups of primary and secondary devices, making said primary devices directly addressable by any of said commonly connected host processors and making said secondary devices not directly addressable by said host processors;

in each of the commonly connected host processors establishing a device table for each of the devices, which tables are separate from the unit control blcoks, storing the addresses of the peripheral devices of the same logical group to which the peripheral device belongs and indicating in each device table whether each of the peripheral devices are primary or secondary devices;

in said peripheral subsystem retentively storing identifications of said logical groups of devices, the addresses of the devices in said logical groups and indicating which of the devices are primary or secondary devices, and status of said cache and programmed control unit;

changing the statut of a peripheral device, programmed control unit or cache of the peripheral sybsystem from within such peripheral subsystem, retentively storing in said subsystem the changed status;

sending an untagged interruption signal from the control unit which identifies a one of the peripheral devices affected by such change in status and indicating in the interruption signal that a device-state transition has occurred;

in each of the commonly connected host processors receiving said untagged interruption signal, operating the host processors to respond to said interruption signal to command the peripheral subsystem to supply status about the device identified in the interruption signal and status of control unit or cache irrespective of what change in status occurred in the subsystem; and

operating the peripheral subsystem to respond to the command to send the change in status to the commanding host processor, then operating the host processor to update its UBS'"'"'s and control tables to reflect the change in subsystem status.

2. In the method set forth in claim 1, further including, the steps of:

establishing a configuration table for the peripheral subsystem including first and second address pointers;

establishing a subsystem control block having a plurality of entries, one of the entires being for each of the devices in the peripheral subsystem and having a third address pointer, making said first address pointer point to the host processor address at which the subsystem control block is established;

making the third address pointer in the entires of the subsystem control block point to the device table established for the device for which the subsystem control block entry was made, making fourth and fifth address pointers in each of the device tables;

establishing one unit control block (UCB) for each device of the subsystem and including a sixth address pointer in said UCB, making said sixth address pointer point to the entry in said configuration table which points to the subsystem control block;

making each of the fourth address pointers point to a UCB established for the device represented by the device table and making each of the fifth address pointers point to a UCB established for a device in the same logical group of devices to which the device belongs; and

establishing an asynchronous operation queue for the subsystem and making the second address pointer point to the asynchronous operation queue.

3. In the method set forth in claim 2, further including the steps of:

generating in the host processor a request for a subsystem asynchronous operation command, establishing an entry in the asynchronous operation queue for the operation command and sending the command to the subsystem; and

receiving from the subsystem an interruption signal including said device-state transition indication for a first one of the devices, then accessing an UCB via said configuration table, subsystem table and device table for a device other than said first one device and performing an operation related to said other device.

4. In a method of operating a peripheral subsystem having a plurality of addressable peripheral devices and a programmed control unit commonly connected to the peripheral devices;

the steps of;

grouping some of the peripheral devices into redundant device groups;

making one of the peripheral devices in each of the groups a primary device and all the rest of the peripheral devices in each group secondary devices;

removing the capability of all secondary devices from being addressable by addresses received by the subsystem from outside the subsystem and within the subsystem making all of the secondary devices addressable through the primary device in the same group;

retentively storing identification and status information of all said groups and peripheral devices assigned to each said group;

receiving into the subsystem a command for a primary device requesting the address of said secondary devices within the group; and

for all of the secondary devices within the group, sending an untagged interrupt to outside the system with the respective address of the secondary devices for indicating that the secondary devices are in the group with the primary device receiving said command.

5. In a peripheral subsystem which is attached to one or more host processors and having a plurality of addressable peripheral devices connected to a shared programmed control;

status and configuration means in the subsystem connected to the peripheral devices and to the programmed control for retentively storing configuration data for the subsystem, including configuration data grouping predetermined ones of the peripheral devices into groups with each group having a primary device and one or more secondary devices, means in the programmed control to maintain addressability of each primary device and making addressability for each of the secondary devices limited to first addressing the primary device in said groups, respectively; and

command execution means in the programmed control for actuating said secondary devices in any one of the groups to emit device-state transition signals to all the host processors as an indication that such secondary devices are in the same group as the primary device in such group, and means in the programmed control for transferring each state transition signal to the host processor.

6. For use in a programmable host processor having addressable storage locations for storing program indicia and control data indicia and means for addressing the addressable storage locations and for controlling asynchronous operations of a connected peripheral subsystem, a set of program indicia having program steps and associated control data structures, including in combination;

vector table indicia containing first and second host processor addresses for first and second control data indicia and being located at a given one of the addressable storage locations;

configuration table indicia at the first address and containing a third address in a plurality of control data entries respectively for a plurality of peripheral subsystems with a first entry being for a first peripheral subsystem having a first subsystem identification (SSID) and being located at a given address offset within the configuration table indicia;

a plurality of subsystems control block indicia located at the third address with subsystem control block indicia for the first peripheral subsystem and containing a fourth address pointer;

a plurality of device table indicia with one device table for each device attached to a host processor within the first peripheral subsystem and having fifth and sixth address pointers, the device table indicia being located at said fourth address;

a plurality of unit control blocks (UCB), one for each device attached to the host processor and each UCB having the second address and entry offset for the peripheral subsystem in which the respective device exists;

each of the control blocks being located at said fifth address for a respective one of the device table indicia, said sixth addresses having a same range of addressability for the UCB'"'"'s as said fifth addresses, predetermined ones of the device tables having a fifth and sixth address with the fifth and sixth address in each of the respective device tables pointing to a different UCB and others of the device tables only having a fifth address;

IOS program indicia for communicating with a subsystem and being coupled to said vector table indicia and having program indicia for receiving SSID signals with interruption signals from a subsystem, and said coupling to the vector table indicia including means for passing the SSID signals thereto; and

AOM program indicia coupled to the IOS program indicia and to all of the control data indicia and having indicia for accessing the vector table indicia for reading the SSID signals, then for selecting a subsystem control block based on the SSID signals and accessing a device table indicia for accessing a fifth and sixth address for identifying a group of UCB'"'"'s addressable by both fifth and sixth addresses whereby a group of devices in the subsystem can be identified.