Twin-rate charging and discharging proportional type cursor position determining device
First Claim
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1. A twin-rate charging and discharging proportional type cursor position determining device comprisinga central processor unit;
- a cursor;
a cursor driving circuit;
a sense ring ciruit composed of a multiple spaced sense rings;
a sense ring switching circuit composed of multiple electronic switches, controlled by the central processor unit to switch the sense rings in the sense ring circuit;
an amplifier circuit connected to the sense ring circuit to amplify voltages detected by the sense rings;
a low pass filter circuit to filter output from the amplifer circuit;
a first comparator circuit which compares output of the low pass filter circuit with a standard voltage and then sends the result of its comparison to the central processor unit;
an analog memory switching circuit controlled by the central processor unit;
an analog memory circuit operable to store output signals from the low pass filter circuit;
a second comparator circuit which compares output signals from the analog memory circuit and then sends the result of the comparison to the central processor unit;
an integrating switch circuit controlled by the central processor unit;
a counter circuit receiving pulse signals and control signals from the single chip central processor unit;
an integrator circuit controlled by the counter circuit to integrate the output signal from the integrating switch circuit;
anintegrating test circuit operable to send a trigger signal to the central procesor unit when the integrator circuit completes integration; and
a latching circuit controlled by the integrating test circuit trigger signal to send the output of the counter circuit to the central processor unit;
wherein the central processor unit drives the sense ring switching circuit to causes voltages detected by the sense ring circuit to proceed via the amplifier circuit and the low pass filter circuit to the first comparator circuit for comparison with a standard voltage; and
wherein if the voltage detected by the sense ring circuit is greater than the standard voltage, the central processor unit drives the analog memory switching circuit to save the largest voltage and second largest voltage in the analog memory circuit for comparison in the second comparator circuit; and
wherein the central processor unit sequentially drives the integrating switch circuit to send the second largest voltage in the analog memory circuit to the integrator circuit for positive integration until the counter circuit counts to a preset value after which the largest voltage in the analog memory circuit is sent to the integrator circuit for negative integration, beginning at the initial value of voltage integrated and continuing until the integrator circuit reaches zero potential.
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Abstract
An electromagnetic digitizer which applies twin rate charging and discharging proportional to determine center position of a cursor. It makes use of the largest and second largest voltages detected by sense rings, the second largest is charged for a standard time, and the largest one is discharged till zero potential, and then the discharge time is compared with sum of the standard time and discharge time, result of which is multiplied by a constant to get center position of the cursor.
9 Citations
5 Claims
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1. A twin-rate charging and discharging proportional type cursor position determining device comprising
a central processor unit; -
a cursor; a cursor driving circuit; a sense ring ciruit composed of a multiple spaced sense rings; a sense ring switching circuit composed of multiple electronic switches, controlled by the central processor unit to switch the sense rings in the sense ring circuit; an amplifier circuit connected to the sense ring circuit to amplify voltages detected by the sense rings; a low pass filter circuit to filter output from the amplifer circuit; a first comparator circuit which compares output of the low pass filter circuit with a standard voltage and then sends the result of its comparison to the central processor unit; an analog memory switching circuit controlled by the central processor unit; an analog memory circuit operable to store output signals from the low pass filter circuit; a second comparator circuit which compares output signals from the analog memory circuit and then sends the result of the comparison to the central processor unit; an integrating switch circuit controlled by the central processor unit; a counter circuit receiving pulse signals and control signals from the single chip central processor unit; an integrator circuit controlled by the counter circuit to integrate the output signal from the integrating switch circuit; anintegrating test circuit operable to send a trigger signal to the central procesor unit when the integrator circuit completes integration; and a latching circuit controlled by the integrating test circuit trigger signal to send the output of the counter circuit to the central processor unit; wherein the central processor unit drives the sense ring switching circuit to causes voltages detected by the sense ring circuit to proceed via the amplifier circuit and the low pass filter circuit to the first comparator circuit for comparison with a standard voltage; and
wherein if the voltage detected by the sense ring circuit is greater than the standard voltage, the central processor unit drives the analog memory switching circuit to save the largest voltage and second largest voltage in the analog memory circuit for comparison in the second comparator circuit; and
wherein the central processor unit sequentially drives the integrating switch circuit to send the second largest voltage in the analog memory circuit to the integrator circuit for positive integration until the counter circuit counts to a preset value after which the largest voltage in the analog memory circuit is sent to the integrator circuit for negative integration, beginning at the initial value of voltage integrated and continuing until the integrator circuit reaches zero potential. - View Dependent Claims (2, 3, 4, 5)
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Specification
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Current AssigneeRadistar Corp.
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Original AssigneeRadistar Corp.
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InventorsChia-Hui, Lin
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Primary Examiner(s)Lall, Parshotam S.
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Assistant Examiner(s)Teska, Kevin J.
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Application NumberUS07/079,167Time in Patent Office683 DaysField of Search178/18, 178/19, 340/709, 364/559, 364/523, 364/518-522US Class Current702/64CPC Class CodesG06F 3/046 by electromagnetic means
