Test control circuit for integrated circuit

• US 4,837,765 A
• Filed: 07/08/1987
• Issued: 06/06/1989
• Est. Priority Date: 07/11/1986
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Suzuki, Takamasa
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Beausoliel, Robert W.
• Application Number:
  US07/071,068
• Time in Patent Office: 699 Days
• Field of Search: 371/25, 371/20, 371/15, 371/68, 371/36, 324/73 R, 324/73 AT
• US Class Current: 714/724
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]

Abstract

For shortening the time period needed for test of component function blocks fabricated on a semiconductor chip and detecting a circuit trouble, there is disclosed a test control circuit for an integrated circuit having a plurality of component blocks including at least two component blocks responsive to respective data signals or a common test signal and achieving predetermined functions, respectively, to produce respective output signals based on the respective data signals or the common test signal, the predetermined functions being identical with one another, comprising (a) a control signal generating circuit responsive to a command signal and capable of producing at least two prohibiting signals applied to the at least two component blocks, respectively (b) a mode selecting circuit responsive to a test mode signal and causing the at least two component blocks to respond to the common test signal, and (c) a logic circuit carrying out a logical operation for the output signals supplied from the at least two component blocks and producing an output signal, wherein each of the at least two component blocks suspends the production of the output signal based on the common test signal in the presence of said prohibiting signal, so that the at least two component blocks are examined in the absence of the prohibiting signal and the logic circuit is examined in the presence of the prohibiting signal.

Claims

1. A test control circuit for an integrated circuit having a plurality of component blocks including at least two component blocks responsive to respective data signals or a common test signal and achieving predetermined functions, respectively, to produce respective output signals based on the respective data signals or the common test signal, said predetermined functions being identical with one another, comprising:

(a) a control signal generating circuit responsive to a command signal and capable of producing at least two prohibiting signals applied to said at least two component blocks, respectively;

(b) mode selecting means responsive to a test mode signal and causing said at least two component blocks to concurrently respond to said common test signal in the absence of said prohibiting signals; and

(c) a logic circuit carrying out a logical operation for the output signals supplied from said at least two component blocks and producing an output signal,

wherein each of said at least two component blocks suspends the production of said output signal based on said common test signal in the presence of said prohibiting signal.

2. A test control circuit as set forth in claim 1, in which said logic circuit carries out an AND operation for the respective output signals supplied from said at least two component blocks.

3. A test control circuit as set forth in claim 1, in which said control signal generating circuit further produces an output control signal and in which said test control circuit further comprises a selector circuit supplied with respective output signals of said component blocks and the output signal of said logic circuit and responsive to said output controlling signal for transferring one of said output signals to output means.

4. A test control circuit as set forth in claim 1, in which the output signal of each of said at least two component blocks consists of a plurality of data bits and in which said logic circuit comprises a plurality of AND gates equal in number to the data bits, wherein each of said AND gates has input nodes equal in number to said at least two component blocks and supplied with the data bits each fed from each of said at least two component blocks.

5. A control circuit as set forth in claim 1, in which the output signal of each of said at least two component blocks consists of a plurality of data bits and in which said logic circuit comprises a plurality of exclusive-NOR gates equal in number to the data bits and an AND gate having input nodes connected to respective output nodes of the exclusive-NOR gates, wherein each of said exclusive-NOR gates has a plurality of input nodes equal in number to said at least two component blocks and supplied with the data bits each fed from each of said at least two component blocks.

6. A test control circuit for an integrated circuit having a plurality of component blocks including at least two component blocks responsive to respective data signals or a common test signal and achieving predetermined functions, respectively, to produce respective output signals based on the respective data signals or the common test signal, said predetermined functions being identical with one another, said test control circuit being capable of carrying out a test mode of operation in accordance with a circuit partial method for concurrently testing said at least two component blocks, comprising:

(a) a control signal generating circuit responsive to a command signal and capable of producing at least two prohibiting signals applied to said at least two component blocks, respectively, said control signal generating circuit further producing an output control signal;

(b) mode selecting means responsive to a test mode signal and causing said test control circuit to be shifted in said test mode of operation in the absence of said prohibiting signals;

(c) a logic circuit carrying out a logical operation for the output signals supplied from said at least two component blocks and producing an output signal; and

(d) a selector circuit supplied with the respective output signals of said component blocks and the output signal of said logic circuit and responsive to said output control signal for transferring one of said output signals to output means,

wherein each of said at least two component blocks suspends the production of said output signal based on said common test signal in the presence of said prohibiting signal.