Paging receiver having battery saving circuit

• US 4,839,639 A
• Filed: 01/12/1987
• Issued: 06/13/1989
• Est. Priority Date: 01/10/1986
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sato, Toshifumi, Oyagi, Takashi
• Primary Examiner(s): Caldwell, Sr., John W.
• Assistant Examiner(s): Holloway, III, Edwin C.
• Application Number:
  US07/002,329
• Time in Patent Office: 883 Days
• Field of Search: 340/825.44, 340/825.47, 340/825.48, 340/311.1, 455/31, 455/38, 455/228, 455/343, 379/56, 379/57, 371/47
• US Class Current: 340/7.34
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: H04W 88/022 Selective call receivers
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A paging receiver includes an improved battery saving circuit which reduces battery usage by powering the radio section and the waveform shaping circuitry only during intervals which include address codewords specific to the given receiver group. Power is not supplied during intervals containing synchronization code signals other than during the first such interval directly following the preamble code. Upon detecting a preamble code during said intervals, power is supplied continuously for a time period sufficient to encompass the synchronization code interval.

Claims

1. A paging receiver comprising:

a receiving section for receiving a paging signal which includes a preamble signal, a synchronization codeward and an address codeword;

switch means for controlling the supply of power to said receiving section in response to a control signal;

means for detecting the preamble signal to produce a preamble detect pulse;

means for detecting said synchronization codeword to produce a synchronization codeword detect pulse;

means for detecting said address codeword to produce an address codeword detect pulse;

error detector means for detecting an error in said address codeword and producing an error detect pulse only when the number of bit errors detected in said codeword is equal to or greater than two, said error detector means being capable of correcting only a one-bit error in said codeword;

sync monitor means for counting said error detect pulses for a predetermined period of time and producing a sync monitor pulse when the number of error detect pulses counted is greater than a predetermined value; and

a controller arranged to receive said preamble detect pulse, said synchronization codeword detect pulse and said sync monitor pulse, said controller comprising means for generating said control signal intermittently at a predetermined interval while in a waiting mode, means for continuously generating said control signal for a predetermined duration in response to the reception of said preamble detect pulse during the intermittent generation of said control signal, means for generating said control signal at a predetermined timing in response to the reception of said synchronization codeword detect pulse during the continuous generation of said control signal, means for generating said control signal at said predetermined interval upon the reception of said sync monitor pulse during the generation of said control signal at said predetermined timing, and means for applying said generated control signal to said switch means.

2. A paging receiver as claimed in claim 1, wherein said controller comprises means for generating said control signal continuously for said predetermined duration upon the reception of said preamble detect signal during the generation of said control signal at said predetermined timing, and means for applying said generated control signal to said switch means.

3. A paging receiver as claimed in claim 2, wherein said address codeword is transmitted in one of a predetermined number of frames, and wherein said predetermined timing includes the timing of said one frame in which said address codeword is transmitted.

4. A paging receiver as claimed in claim 1, further comprising means for generating an alert signal in response to said address codeword detect pulse.

5. A method of decreasing the battery usage of a receiver, comprising the steps of:

supplying power to a predetermined section of said receiver in response to a control signal;

generating said control signal intermittently while said receiver is waiting for a paging signal;

generating said control signal at a predetermined timing in response to the detection of a synchronization codeword in said paging signal;

detecting bit errors in an address codeword which is contained in said paging signal while said control signal is being operated at said predetermined timing, and, only when the number of bit errors is equal to or greater than two, providing an error detect pulse, and only when the number of bit errors is less than two, correcting said bit error; and

counting said error detect pulses for a predetermined period of time, and, when the number of error detect pulses counted is greater than a predetermined value, replacing the generation of said control signal at said predetermined timing with said intermittent generation.

6. A method as claimed in claim 5, further comprising the steps of:

generating said control signal continuously for a predetermined duration when a preamble signal in said paging signal is detected;

detecting said synchronization codeword while said control signal is being continuously for said predetermined duration; and

generating said control signal continuously for a predetermined duration when said preamble signal is detected while said control signal is being generated at said predetermined timing.

7. A paging receiver having a battery saving circuit and constructed to receive and process a paging signal, said paging receiver comprising;

controller means including error detection means for detecting bit errors in an address codeword contained in said paging signal to produce an error detect signal only when the number of errors is equal to or greater than two, and to correct said bit errors only when the number of errors is less than two;

sync monitor means for counting said error detect signals for a predetermined period of time and providing a sync monitor signal when the number of error detect signals detected is greater than a predetermined value, and control means for controlling said battery saving circuit in response of said sync monitor signal output by said error detection means.

8. A paging receiver having a battery saving circuit and constructed to receive and process a paging signal, said paging receiver comprising;

controller means, including;

means for detecting a preamble signal contained in said paging signal;

error detection means for detecting bit errors in an address code contained in said paging signal, to produce an error detect signal only when the number of errors is equal to or greater than two, and to correct said bit errors only when the number of errors is less than two;

sync monitor means for counting said error detect signals for a predetermined period of time, and for providing a sync monitor signal when the number of error detect signals counted is greater than a predetermined value; and

control means for outputting a signal for controlling said battery saving circuit in response to said sync monitor signal, and for outputting a signal for enabling a synchronization codeword detecting section in response to said sync monitor signal and a preamble detect signal output by said preamble detect means.