Data transmission system with data verification
First Claim
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1. In a system for selectively obtaining data from a plurality of remotely located data indicating devices, including an interrogate source and a plurality of transponders each including information processing circuit means including signal receiver means, signal transmitter means and signal processor means, each transponder being associated with a different one of the data indicating devices, the improvement comprising:
- means at said interrogate source for transmitting an interrogate signal for effecting the readout of a selected indicating device, said interrogate signal including single cycles of binary signals of first and second time durations respectively in a coded sequence of signals comprising a multibit sync word and a multibit address word for addressing a selected transponder, and each of said transponders further comprising control circuit means including cycle timing circuit means, delay circuit means, and delay override circuit means, said cycle timing circuit means generating a periodically recurring inhibit signal of a predetermined time duration defining a low-power idle mode in which said information processing circuit means is inhibited, said delay circuit means controlling said cycle timing circuit means to delay the generation of each inhibit signal thereby providing a time interval between successive inhibit signals defining a processing mode in which said information processing circuit means is enabled, said information processing circuit means when in said processing mode operating to detect an interrogate signal, and characterized in that the duration of said inhibit signal is considerably longer than said processing mode duration in the absence of an interrogate signal, said signal receiver means including signal edge detecting circuit means enabled by said control circuit means to operate in said processing mode to provide an output signal for each cycle of the binary signals which comprise the interrogate signal, each output signal corresponding to the leading edge of a different one of the binary signals and the elapsed time between successive output signals being indicative of the time duration and the binary state of the bit of the interrogate signal detected, said signal processor means being enabled by said control circuit means to operate in said processing mode and being programmed to respond to the output signals provided by said signal edge detecting circuit means to control said delay circuit means to extend the duration of said processing mode and being further programmed to verify the validity of each bit of the received interrogate signal by determining the elapsed time between successive ones of the output signals provided by said signal edge detecting circuit means and comparing the value of elapsed time determined for each bit with stored reference signals representative of acceptable tolerances on said respective time durations of said detected bits, to determine whether each incoming bit is a first binary state, a second binary state or an invalid bit, said signal processor means accumulating a count of invalid bits and enabling said delay override circuit means to cause said cycle timing circuit means to generate its inhibit signal whereby said information processing circuit means is transferred immediately from the processing mode to the lowpower idle mode, thereby terminating further processing during detection if a predetermined number of invalid bits is detected before said interrogate signal ends, said signal processor means being further programmed to store detected valid bits and compare the same with stored reference signals representing said sync word of said interrogate signal and to cause said cycle timing circuit means to generate said inhibit signal to return said information processing circuit means to said low power idle mode if said sync word is not detected in a predetermined number of bits, and said signal processor means enabling said signal transmitter means to transmit data signals associated with the associated data indicating device only upon verification that the sync word of the received interrogate signal is received and the associated address word is received.
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Abstract
A system for selectively obtaining information from a plurality of remotely located data indicating devices includes an interrogate source and a plurality of transponders each associated with a different one of the data indicating devices. The interrogate source transmits an interrogate signal for effecting the readout of a selected indicating device, the interrogate signal being a high frequency carrier amplitude modulated with a pair of low frequency signals to represent an eight bit sync code word, a four bit command word and a twenty-eight bit identification code word for addressing a selected transponder. Each transponder includes a receiver which detects the low frequency modulating signals and generates a short duration pulse corresponding to the leading edge of each modulating signal, a processor operating under program control to check on a bit-by-bit basis each bit of the sync code word and of the identification code word as it is received by timing the duration between the receiver generated pulses, and to thereafter compare the first eight bits with a stored sync word and the bits corresponding to the identification word with a stored identification word, the processor responding to the interrogate signal to activate a transmitter to transmit the information provided by the associated indicating device only if the signals detected by the receiver are within a preselected range of frequencies and if a valid sync word and a valid identification word are received.
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Citations
5 Claims
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1. In a system for selectively obtaining data from a plurality of remotely located data indicating devices, including an interrogate source and a plurality of transponders each including information processing circuit means including signal receiver means, signal transmitter means and signal processor means, each transponder being associated with a different one of the data indicating devices, the improvement comprising:
- means at said interrogate source for transmitting an interrogate signal for effecting the readout of a selected indicating device, said interrogate signal including single cycles of binary signals of first and second time durations respectively in a coded sequence of signals comprising a multibit sync word and a multibit address word for addressing a selected transponder, and each of said transponders further comprising control circuit means including cycle timing circuit means, delay circuit means, and delay override circuit means, said cycle timing circuit means generating a periodically recurring inhibit signal of a predetermined time duration defining a low-power idle mode in which said information processing circuit means is inhibited, said delay circuit means controlling said cycle timing circuit means to delay the generation of each inhibit signal thereby providing a time interval between successive inhibit signals defining a processing mode in which said information processing circuit means is enabled, said information processing circuit means when in said processing mode operating to detect an interrogate signal, and characterized in that the duration of said inhibit signal is considerably longer than said processing mode duration in the absence of an interrogate signal, said signal receiver means including signal edge detecting circuit means enabled by said control circuit means to operate in said processing mode to provide an output signal for each cycle of the binary signals which comprise the interrogate signal, each output signal corresponding to the leading edge of a different one of the binary signals and the elapsed time between successive output signals being indicative of the time duration and the binary state of the bit of the interrogate signal detected, said signal processor means being enabled by said control circuit means to operate in said processing mode and being programmed to respond to the output signals provided by said signal edge detecting circuit means to control said delay circuit means to extend the duration of said processing mode and being further programmed to verify the validity of each bit of the received interrogate signal by determining the elapsed time between successive ones of the output signals provided by said signal edge detecting circuit means and comparing the value of elapsed time determined for each bit with stored reference signals representative of acceptable tolerances on said respective time durations of said detected bits, to determine whether each incoming bit is a first binary state, a second binary state or an invalid bit, said signal processor means accumulating a count of invalid bits and enabling said delay override circuit means to cause said cycle timing circuit means to generate its inhibit signal whereby said information processing circuit means is transferred immediately from the processing mode to the lowpower idle mode, thereby terminating further processing during detection if a predetermined number of invalid bits is detected before said interrogate signal ends, said signal processor means being further programmed to store detected valid bits and compare the same with stored reference signals representing said sync word of said interrogate signal and to cause said cycle timing circuit means to generate said inhibit signal to return said information processing circuit means to said low power idle mode if said sync word is not detected in a predetermined number of bits, and said signal processor means enabling said signal transmitter means to transmit data signals associated with the associated data indicating device only upon verification that the sync word of the received interrogate signal is received and the associated address word is received.
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Specification
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Current AssigneeNorthern Illinois Gas Company (Southern Company)
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Original AssigneeNorthern Illinois Gas Company (Southern Company)
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InventorsMartell, Dennis J., Overmyer, Steven A., Batz, James E.
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Primary Examiner(s)Weldon, Ulysses
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Application NumberUS07/106,938Time in Patent Office614 DaysField of Search340/870.02, 340/825.02, 340/825.03-825.14, 340/825.54, 340/825.44, 340/825.47, 340/825.48, 340/310 CP, 370/60, 370/85, 370/92, 370/93, 370/94, 370/99, 370/88, 375/113, 375/114, 375/94US Class Current340/10.31CPC Class CodesG01D 4/006 Remote reading of utility m...H04Q 9/14 Calling by using pulsesY02B 90/20 Smart grids as enabling tec...Y04S 20/30 Smart metering, e.g. specia...
