Monolithic semi-custom LSI

• US 4,839,820 A
• Filed: 07/01/1985
• Issued: 06/13/1989
• Est. Priority Date: 07/02/1984
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Kazuyuki, Kinoshita, Tsuneo
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): HERNDON, HEATHER R
• Application Number:
  US06/750,472
• Time in Patent Office: 1,443 Days
• Field of Search: 364/488-491, 357/40, 357/45, 357/51, 357/68, 307/303
• US Class Current: 716/126
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/923 with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Abstract

According to an large scale integration (LSI) system, different types of macrocells which are required to establish a predetermined system and which have a first-layer of wiring and a glue circuit for compensating for the functions not provided by the marcrocells alone, are formed on a single semiconductor substrate. The different types of macrocells correspond to different types of independent LSIs constituting the predetermined system. The macrocells have the same main circuits as those of the independent LSIs. The pattern configuration of the main circuits of the macrocells adopts the patterns of the corresponding independent LSIs. A second-layer of wiring is connected between the macrocells and between the macrocells and the glue circuit as needed.

Claims

1. A semi-custom large scale integration circuit comprising:

a substrate;

a plurality of macrocells formed in said substrate each having bonding pads and each including a plurality of individual customized bulk semiconductor elements arranged in conventional independent LSI mask patterns and interconnected by a first layer of wiring connected to said bonding pads, said macrocells having different sets of operating characteristics;

glue circuit means for converting said sets of operating characteristics to permit interactive operation of said plurality of macrocells, said glue circuit means comprising a plurality semi-custom integrated circuits formed in said substrate of a plurality of standard cells arranged in a array; and

a second layer of wiring interconnecting said macrocells and said glue circuit means so as to provide for operation of said large scale integration circuit.

2. A semi-custom large scale integration circuit as recited in claim 1 further comprising a clock bus, a local bus, a control bus, an address bus, and a data bus each coupled to said macrocells and to said glue circuit means.

3. A semi-custom large scale integration circuit according to claim 2, wherein said glue circuit means includes a wait state logic coupled to said clock bus and said control bus, an address latch coupled to said local bus and said address bus, a data buffer coupled to said local bus and said data bus, a memory control logic coupled to said control bus, a parity circuit circuit coupled to said control bus and said data bus, an I/O chip selecting circuit coupled to said address bus, a DMA page register coupled to said address bus and said data bus, a DMA address latch coupled to said address bus and said data bus, a data bus enable decoder coupled to address bus, a serial/parallel converter coupled to said macrocells, and a non-maskable interrupt logic coupled to said local bus.

4. A semi-custom large scale integration circuit according to claim 2, wherein said plurality of macrocells comprises a clock generating circuit coupled to said clock bus;

a bus controller coupled to said local bus and said control bus;

an interrupt controller coupled to said local bus, control bus, said address bus, and said data bus;

a direct memory access controller coupled to said said control bus, said address bus, and said data bus;

a timer coupled to said control bus, said address bus, and said data bus; and

input/output port coupled to said control bus, said address bus, and said data bus;

a cathode ray tube controller coupled to said control bus, said address bus, and said data bus; and

a floppy disk controller coupled to said control bus, said address bus, and said data bus.