Automatic cell-layout arranging method and apparatus for polycell logic LSI

• US 4,839,821 A
• Filed: 12/23/1986
• Issued: 06/13/1989
• Est. Priority Date: 02/25/1986
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Murakata, Masami
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Cosimano, Edward R.
• Application Number:
  US06/945,854
• Time in Patent Office: 903 Days
• Field of Search: 364/300, 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

In an automatic cell-layout arranging system for a polycell logic LSI, polycells are initially arranged in the form of cell arrays on a chip substrate. Connection paths for wiring lines among the polycells are then determined in accordance with cell-wiring requirements, so as to maximally satisfy a predetermined object function, thereby obtaining an LSI logic circuit capable of performing the desired function. A processor unit calculates a first number "N" of wiring lines actually extending through each of the cell arrays, and a second number "ml" representing an allowable number of through-lines for each cell array. Thereafter, this unit calculates a third number "K" representing the difference "ml-N" between the first and second numbers. When a certain cell array where the third number "K" is less than zero is included in the cell arrays, the standard cells are rearranged on the chip substrate such that the third number "K" is increased to zero or more than zero, thereby maximally eliminating the need to use through-cells for passing wiring lines through the cell arrays.

Claims

1. A computer-controlled apparatus for automatically designing a cell-layout of a semiconductor logic LSI device having standard cells, on a ship substrate, said apparatus comprising:

(a) input means for receiving design data including an object function and cell-wiring requirements defining a desired logic function of said LSI device; and

(b) processor means connected to said input means, for arranging said standard cells in cell arrays, and for designing electrical connection of said standard cells in accordance with said cell-wiring requirements, so as to maximally satisfy said object function, thereby obtaining an LSI logic circuit, said processor means comprising,

first means for calculating a first number "N" of wiring lines which actually extend through each array of standard cells initially arranged on said chip substrate,

second means for calculating a second number "m1" of wiring lines that are allowed to extend through each array of standard cells initially arranged on said chip substrate,

third means for calculating a third number "K" representing a difference "m1-N" between said first and second numbers of each cell array, and for determining whether or not said cell arrays include a certain cell array where said third number "K" is less than zero, and

fourth means for rearranging said standard cells on said chip substrate, when it is found that said certain cell array is included in said cell array, such that said third number "K" of said certain cell array is increased to zero or to more than zero, thereby minimizing lengths of the cell arrays and ultimately minimizing a size of said chip substrate, said fourth means stopping the designing execution if said third number "K" is zero or more than zero, and for causing the above calculating process executed by said first to third means to be repeated if said third number "K" remains negative after the rearrangement is executed, and adding to said certain cell array a corresponding number of through-cells when said number "K" still remains negative even after rearrangement is executed repeatedly

2. The apparatus according to claim 1, wherein said processor means further comprises:

fifth means for calculating a length "L" of each of said cell arrays, to specify a cell array having the maximum length, and for calculating differences "D" between said maximum length and the lengths of the remaining cell arrays; and

sixth means for calculating a fourth number "m2" of wiring lines which can extend on that surface area of said chip substrate which corresponds to the calculated length difference "D" of each of said remaining cell arrays.

3. The apparatus according claim 2, wherein said third means performs an operation defined by the following equation, to calculate said third number "K" for each cell array:

space="preserve" listing-type="equation">K=(m1+m2)-N.

4. A method for automatically designing a cell-layout of a semiconductor logic LSI device having standard cells, on a chip substrate, said method comprising the steps of:

(a) inputting design data including an object function and cell-wiring requirements defining a desired logic function of said LSI device;

(b) arranging said standard cells in cell arrays, on said chip substrate; and

(c) determining electrical connection paths for wiring lines among said standard cells, in accordance with said cell-wiring requirements, so as to maximally satisfy said object function, thereby obtaining an LSI logic circuit, said connection paths-determining step comprising,

calculating a first number "N" of wiring lines which actually extend through each array of standard cells initially arranged on said chip substrate,

calculating a second number "m1" of wiring lines that are allowed to extend through each array of standard cells initially arranged on said chip substrate,

calculating a third number "K" representing a difference "m1-N" between said first and second numbers of each cell array, to determine whether or not said cell arrays include a certain cell array where said third number "K" is less than zero, and

rearranging said standard cells on said chip substrate, when it is found that said certain cell array is included in said cell array, such that said third number "K" of said certain cell array is increased to zero or to more than zero, thereby minimizing lengths of the cell arrays and ultimately minimizing a size of said chip substrate and stopping the designing execution if said third number "K" is zero or more than zero, and for causing the above calculating process executed by said first to third means to be repeated if said third number "K" remains negative after the rearrangement is executed.

5. The method according to claim 4, wherein said connection paths-determining step further comprises:

calculating a length "L" of each of said cell arrays, to specify a cell array having the maximum length,

calculating differences "D" between said maximum length and the lengths of the remaining cell arrays; and

calculating a fourth number "m2" of wiring lines which can extend on that surface area of said chip substrate which corresponds to the calculated length difference "D" of each of said remaining cell arrays.

6. The method according to claim 5, wherein an operation defined by the following equation is performed to calculate said third number "K" for each cell array:

space="preserve" listing-type="equation">K=(m1+m2)-N.