Data card circuits

• US 4,841,133 A
• Filed: 03/30/1988
• Issued: 06/20/1989
• Est. Priority Date: 06/30/1987
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hudson, Peter D., Bron, Michel, Gercekci, Anil
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US07/175,390
• Time in Patent Office: 447 Days
• Field of Search: 235/380, 235/492
• US Class Current: 235/492
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
• CPC Class Codes: G06K 19/07372 by detecting tampering with the circuit
• CPC Class Codes: G06Q 20/3558 Preliminary personalisation for transfer to user
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

An integrated circuit for a data or "smart" card includes a non-volatile memory (8) having a transport code preprogrammed therein, control circuitry (10), a comparator (24) for comprising an externally-applied code and the transport code, and a fuse (26) which is blown if the two codes match thereby allowing the card to be initialised with a personal identification number and initial credit values. A second fuse (28) may also be provided which is blown if the two codes do not match and sensing means (32, 34) sense the status of the two fuses (26, 28) and block any further attempts to initialise the card if the second fuse (28) is blown and the first fuse (26) is not.

Claims

1. A data card of the type comprising an integrated circuit on a semiconductor chip embedded in a plastic card, the circuit including a non-volatile memory having a transport code preprogrmamed therein, control circuitry for controlling the circuit, a comparator having a first input coupled to an input node of the circuit for receiving an externally-applied code and a second input coupled to said memory for comparing said externally-applied and transport codes, and a first irreversible switch coupled to an output of the comparator such that said first irreversible switch is actuated if the externally-applied and transport codes match.

2. A data card according to claim 1 further comprisng first sensing means coupled between said control circuitry and said first switch for sensing whether said first switch has been actuated, whereby the transport code is deleted from the memory and initialisation of the memory is enabled by the control circuitry if the first switch has been actuated.

3. A data card according to claim 2 further comprising blocking means coupled to said control circuitry for preventing the memory from being read or programmed if said first switch has not been actuated.

4. A data card according to claim 2 wherein initiatisation of the memory includes programming an inital value of a counter.

5. A data card according to claim 2 wherein initialisation of the memory includes programming a personal security code into the memory.

6. A data card according to claim 1 wherein said memory is an EEPROM.

7. A data card according to claim 1 further comprising a second irreversible switch coupled to an output of the comparator such that the irreversible switch is actuated if the externally-applied and transport codes do not match.

8. A data card according to claim 7 further comprising second sensing means coupled between said control circuitry and said second switch for sensing whether said second switch has been actuated and disabling means coupled to said control circuitry for disabling the circuit if said second switch has been actuated.

9. A data card according to claim 7 wherein said first and second switches are coupled in parallel to the output of the comparator such that the output of a signal from the comparator causes either the first or the second switch to be actuated.

10. A data card according to claim 1 wherein said first irreversible switch is a fuse.

11. A data card according to claim 6 wherein said second irreversible switch is a fuse.

12. A data card according to claim 10 wherein said first and second irreversible switch are fuses having the same sensitivity such that the same current is required to blow either fuse.

13. A data card according to claim 1 further comprising test means for simulating the status of a said irreversible switch whereby said circuit may be tested without activating said irreversible switch.

14. A data card according to claim 13 wherein said test means comprises a logic circuit and is enabled by a test signal.

15. A data card according to claim 14 wherein said test means comprises a latch having an output coupled to a first input of an AND-gate, a second input of the AND gate being coupled to receive the test signal, and an EXCLUSIVE OR-gate having a first input coupled to the output of said AND-gate, a second input coupled to said irreversible switch.

16. A data card according to claim 14 wherein said test means comprises a latch having an output coupled to a first input of a first AND-gate, a second input of the first AND-gate geing coupled to receive the test signal, a second AND-gate having a first input coupled to said irreversible switch, a second input coupled to receive the test signal via an inverter, and an OR-gate coupled to receive at its inputs, outputs from the two AND-gates.

17. A data card according to claim 14 comprising first and second said test means for simulating the status of first and second irreversible switches respectively.

18. A data card according to claim 13 wherein said test means includes a third irreversible switch which is actuated on completion of the test.

19. A data card according to claim 18 wherein said third irreversible switch is a fuse.