Control processor for controlling a peripheral unit

• US 4,841,440 A
• Filed: 04/26/1984
• Issued: 06/20/1989
• Est. Priority Date: 04/26/1983
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yonezu, Kazuya, Matsumoto, Keiji
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US06/604,274
• Time in Patent Office: 1,881 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands

Abstract

A peripheral control processor for controlling data communication between a host processor and a peripheral unit in response to command signals applied to the host processor. The peripheral control processor has an idle time or a standby condition when data communication is not required. When the peripheral control processor is idle or in a standby condition, a control circuit, within the processor inhibits a control clock signal which activates transistor elements of an internal circuit in the processor. Therefore, unnecessary power comsumption is reduced during idle time or a standby condition. Further, the control circuit can produce the inhibition signal by using the command signals used for data communication. Therefore, no new signals or terminals are required for applying input signals to the control circuit.

Claims

1. A peripheral control processor for use with a host processor and a peripheral unit, said peripheral control processor receiving an external clock signal and an external reset signal, said peripheral control processor comprising:

a first terminal for receiving said external clock signal;

a second terminal for receiving said external reset signal to initialize said peripheral control processor;

a third terminal for receiving a chip select signal;

a fourth terminal for receiving a reading signal or a writing signal;

a data communication circuit, coupled to said first to fourth terminals, for transferring data between said host processor and said peripheral unit on the basis of timing control by said external clock signal, said data communication circuit being enabled by said chip select signal and initialized by said external reset signal, said data communication circuit transferring said data from said host processor to said peripheral unit in response to said writing signal and from said peripheral unit to said host processor in response to said reading signal; and

a control circuit coupled between said first terminal and said data communication unit and connected to said second, third and fourth terminals, said control circuit permitting said external clock signal to be supplied to said data communication circuit when both of said chip select signal and said reading signal or said writing signal are received, and inhibiting application of said external clock signal to said data communication circuit when said external reset signal is received, wherein said data communication circuit it initialized and power consumption of said data communication circuit is reduced in response to said external reset signal.

2. A peripheral control processor as claimed in claim 1, wherein said data communication circuit includes a plurality of latch circuits driven by said clock signal.

3. A peripheral control processor as claimed in claim 1, wherein said control circuit includes a flip-flop circuit which is set by said reset signal and reset by said chip select signal and said reading signal or said writing signal, and a gate circuit receiving said clock signal and an output of said flip-flop circuit.

4. A peripheral control processor as claimed in claim 1, wherein said data communication circuit, said first control circuit and said second control circuit are integrated on a semiconductor chip.

5. A peripheral control processor receiving an external clock signal, said peripheral control processor comprising:

first means for transferring data from a host processor to a peripheral unit;

second means for receiving said external clock signal from said host processor;

third means for receiving first and second command signals supplied by said host processor, wherein said first command signal indicates a start of a data transfer and said second command signal indicates initialization of said peripheral control processor;

fourth means, coupled to said first and third means, for controlling said first means to enable the data transfer in response to said first command signal, and to reset said first means in response to said second command signal; and

fifth means, coupled to said first, second, and third means for applying said external clock signal to said first means in response to said first command signal and for inhibiting application of said external clock signal to said first means in response to said second command signal, wherein said first means is reset and power consumption of said first means is reduced in response to said second command signal.

6. A peripheral control processor comprising:

a data communication circuit for transferring data between a host processor and a peripheral unit on the basis of timing control by a clock signal received from said host processor;

a first control circuit coupled to said data communication circuit and generating a control signal to activate said data communication circuit in response to a plurality of signals received from the host processor;

means for applying said clock signal to said data communication circuit;

means responsive to a reset signal received from said host processor for initializing said data communication circuit; and

a second control circuit, coupled to said clock signal applying means and said reset signal responsive means, for generating an inhibition signal to inhibit application of said clock signal to said data communication circuit when said reset signal is received, wherein said data communication circuit is reset and power consumption in said data communication circuit is reduced in response to said reset signal.

7. A peripheral control processor for use with a host processor and a peripheral unit, said peripheral control processor receiving an external clock signal and an external reset signal, said peripheral control processor comprising:

a first terminal for receiving said external clock signal;

a second terminal for receiving said external reset signal;

a third terminal for receiving a chip select signal from said host processor;

a fourth terminal for receiving a reading signal or a writing signal from said host processor;

a data communication circuit, coupled to said first to fourth terminals, for transferring data between said host processor and said peripheral unit on the basis of timing control by said clock signal, said data communication circuit being enabled by said chip select signal and initialized by said reset signal, said data communication circuit transferring said data from said host processor to said peripheral unit in response to said writing signal and from said peripheral unit to said host processor in response to said reading signal; and

a control circuit coupled between said first terminal and said data communication circuit and connected to said second, third and fourth terminals, said control circuit permitting said clock signal to be supplied to said data communication circuit when both of said chip select signal and said reading signal or said writing signal are received, and inhibiting application of said clock signal to said data communication circuit when said reset signal is received;

said control circuit including a first logic gate receiving said chip select signal and said reading signal or writing signal to produce a first control signal when said chip select signal and said reading signal or said writing signal are received, a flip-flop circuit having first and second states, means responsive to said reset signal for placing said flip-flop in said first state, means responsive to said first control signal for placing said flip-flop in said second state, and a second logic gate receiving said clock signal and coupled to an output of said flip-flop for transferring said clock signal to said data communication circuit in response to said second state of said flip-flop, and for inhibiting said external clock signal from being transferred to said data communication circuit in response to said first state of said flip-flop.

8. A peripheral control processor as claimed in claim 7, wherein said first logic gate is an AND gate.

9. A peripheral control processor as claimed in claim 7, wherein said second logic gate is an AND gate.