Method of selective via-hole and heat sink plating using a metal mask

• US 4,842,699 A
• Filed: 05/10/1988
• Issued: 06/27/1989
• Est. Priority Date: 05/10/1988
• Status: Expired due to Term

• Current Assignee: Avago Technologies Wireless IP Singapore Pte Limited (Broadcom, Inc.)
• Original Assignee: Avantek Inc. (HP Inc.)
• Inventors: Hua, Chang-Hwang, Chan, Simon S., Day, Ding-Yuan S.
• Primary Examiner(s): Tufariello, T. M.
• Application Number:
  US07/192,199
• Time in Patent Office: 413 Days
• Field of Search: 204/15, 204/38.1, 204/38.4
• US Class Current: 205/126
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:

(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;

(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;

(c) forming via-holes through said wafer;

(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and

(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.

Claims

1. A method for selective plating of via-holes and heat sinks associated with a semiconductor wafer having a first side and a second side by the use of a metal mask comprising the steps of:

(a) coating the first side of the wafer with an insulating layer to prevent electroplating on the first side;

(b) patterning a metal mask on the second side of the wafer for defining the areas where plating should not occur;

(c) etching via-holes through the wafer from the second side of the wafer;

(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and

(e) electrolytically plating the resulting wafer so that the walls of the via-holes are plated and heat sinks are simultaneously plated on the second side of the wafer.

2. The method according to claim 1 wherein the electrolytic plating step further comprises electroplating the resulting wafer while ultrasonically agitating the electrolyte to ensure sufficient electrolyte transport into the via-holes for uniform plating.

3. The method according to claim 1 wherein the step of depositing the thin conductive film comprises electroless plating the thin conductive film on the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask.

4. The method according to claim 1 wherein the step of patterning the metal mask consists of selectively applying a first layer of a noble metal on desired areas of the second side of the wafer and selectively covering this first layer with a second layer of a protective metal which readily forms an inert and impervious oxide in air.

5. The method according to claim 4 wherein the step of applying the first layer of the metal mask comprises applying a conductive metal which does not oxidize in air and the step of applying the second layer of the metal mask comprises applying titanium.

6. The method according to claims 4 or 5 wherein the first layer of the metal mask is formed of gold.

7. The method according to claim 4 wherein the step of patterning the metal mask comprises the steps of selectively depositing a first layer of the metal mask on desired areas of the second side of the wafer, said first layer being composed of a metal with good adhesion to the wafer, followed by selectively depositing a second layer of the metal mask of a noble metal which does not oxidize in air, overlaying the first layer, and followed by selectively depositing a third layer of the metal mask of protective metal which overlays the second layer, the third layer forming an inert and impervious oxide in air.

8. The method according to claim 7 wherein the wafer has one or more metal pads on its first side and the step of etching the via-holes comprises etching the holes through the wafer to a depth such that they terminate at the pads.

9. The method according to claim 1 further comprising the initial step of forming at least one conductive pad on said first side, said pad having a top surface and a bottom surface, said bottom surface facing the first side of the wafer, and then forming the insulating layer over said first side of said wafer and said pad.

10. The method according to claim 9 wherein the step of etching the via-holes comprises etching the holes through the wafer to a depth such that they terminate at the pads.

11. The method according to claims 1 or 9 wherein the step of forming the insulating layer comprises forming a layer of wax.

12. A method of fabricating a semiconductor wafer with electroplated via-holes and heat sinks as recited in claim 1 wherein the via-holes have a depth to diameter ratio of up to 3.