Method of selective via-hole and heat sink plating using a metal mask
First Claim
1. A method for selective plating of via-holes and heat sinks associated with a semiconductor wafer having a first side and a second side by the use of a metal mask comprising the steps of:
- (a) coating the first side of the wafer with an insulating layer to prevent electroplating on the first side;
(b) patterning a metal mask on the second side of the wafer for defining the areas where plating should not occur;
(c) etching via-holes through the wafer from the second side of the wafer;
(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and
(e) electrolytically plating the resulting wafer so that the walls of the via-holes are plated and heat sinks are simultaneously plated on the second side of the wafer.
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Accused Products
Abstract
A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:
(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;
(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;
(c) forming via-holes through said wafer;
(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and
(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.
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Citations
12 Claims
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1. A method for selective plating of via-holes and heat sinks associated with a semiconductor wafer having a first side and a second side by the use of a metal mask comprising the steps of:
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(a) coating the first side of the wafer with an insulating layer to prevent electroplating on the first side; (b) patterning a metal mask on the second side of the wafer for defining the areas where plating should not occur; (c) etching via-holes through the wafer from the second side of the wafer; (d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and (e) electrolytically plating the resulting wafer so that the walls of the via-holes are plated and heat sinks are simultaneously plated on the second side of the wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification