Information transfer system for transferring binary information

• US 4,843,539 A
• Filed: 01/29/1987
• Issued: 06/27/1989
• Est. Priority Date: 02/06/1986
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Bury, Joachim
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/008,783
• Time in Patent Office: 880 Days
• Field of Search: 365/78, 377/75, 370/86, 364/200 MS File, 364/900 MS File
• US Class Current: 714/43
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/21032 Controlled module in a ring, each module detects its own address
• CPC Class Codes: G05B 2219/25133 Serial parallel conversion
• CPC Class Codes: G05B 2219/25171 Serial, RS232
• CPC Class Codes: G05B 2219/25178 Serial communication, data, also repeater
• CPC Class Codes: G05B 2219/25267 Shift register
• CPC Class Codes: G05B 2219/25296 Identification module, type connected I-O, device
• CPC Class Codes: G05B 2219/25458 Opto isolation, optical separation

Abstract

An information transfer system for transferring binary information between a central unit and modular peripheral assemblies via a bus system. The bus system is designed as a serial ring shift register. An interface unit which permits parallel transfer of the individual binary information is interposed between the peripheral assembly and the bus.

Claims

1. An information transfer system for transferring binary information between a central unit and a plurality of modular peripheral assemblies via a bus system, wherein the bus system comprises a serial ring, and further comprises an interface unit comprising a shift register of said serial ring associated with each peripheral assembly which permits parallel tranfer of the binary information between each peripheral assembly and the bus system, each said interface unit being disposed in the serial ring and having parallel outputs and inputs coupled to a respective peripheral assembly, said bus system further comprising a plurality of control lines for controlling said interface units, each said interface unit comprising two sub-units, each sub-unit comprising four information bits, and further comprising first switching means provided at terminal ends of each interface unit allowing serial outputs and inputs of said interface units to be coupled together to form a ring shift register, and further comprising second switching means provided at said terminal ends for coupling said interface units together to form an enlarged ring shift register.

2. The system recited in claim 1, wherein said interface unit comprises at least one integrated circuit.

3. The system recited in claim 2, wherein said integrated circuit comprise CMOS technology.

4. The system recited in claim 1, wherein each interface unit is provided in a plug-in location for the peripheral assembly.

5. The system recited in claim 1, wherein four control lines are provided coupled to each interface unit.

6. The system recited in claim 5, wherein, of the four control lines, one sets the bus system to a defined starting state (CLEAR), a second one switches the function of the serial ring shift register from serial shifting to parallel transfer (LATCH), a third one carries out switching between peripheral assemblies and parallel inputs of the shift register (IDENT) and the fourth one provides an operating clock frequency (CLOCK).

7. The system recited in claim 6, wherein the third control line (IDENT) determines the type of function by a code stored in the respective peripheral assembly.

8. The system recited in claim 6, wherein the interface unit comprises a tristate write/read amplifier.

9. The system recited in claim 8, wherein the interface unit reads back the output of the tristate write/read amplifier.

10. The system recited in claim 1, wherein each sub-unit of the serial ring shift register comprises an additional fifth information bit which serves for self-monitoring of the bus system.

11. The system recited in claim 10, wherein the fifth information bit is generated by a respective peripheral assembly, said respective peripheral assembly feeding information to the serial ring shift register.

12. The system recited in claim 11, wherein the fifth information bit controls the parallel transfer of the binary information under control of said third control line.

13. The system recited in claim 1, wherein the switching means comprises tristate amplifiers.

14. The system recited in claim 1, wherein each interface unit comprises a plurality of tristate amplifiers which are operative as a function of a further interface unit plugged parallel to the respective interface unit.

15. The system recited in claim 1, wherein each sub-unit of the enlarged ring shift register can be shunted by a shift register with a bit number larger than that of the sub-unit.

16. The system recited in claim 15, wherein at the shunting point, a device for obtaining a predetermined signal state is provided which is operative if the shift register is removed.

17. The system recited in claim 15, wherein a blocking device for blocking the transfer of disturbed ring shift register information is provided.

18. A method for detecting and correcting an interruption of a data ring of an information transfer system for transferring binary information between a central unit and a plurality of modular peripheral assemblies via a bus system wherein the bus system comprises a serial ring and further having an interface unit comprising a shift register of said serial ring associated with each peripheral assembly which permits parallel transfer of the binary information between each peripheral assembly and the bus system, each said interface unit being disposed in the serial ring and having a serial input and serial output connected in the serial ring and parallel outputs and inputs coupled to a respective peripheral assembly, said bus system further comprising a plurality of control lines for controlling said interface units, and further comprising means for obtaining a predetermined signal state which is operative if a shift register is removed from the data ring, wherein, if a shift register is removed from the data ring and if the predetermined signal state become effective, the central unit recognizes the interruption by means of the signal state and carries out an identification cycle for reactiving a switched-off sub-unit in the interface without influencing starting signal states on the data ring.

19. A method for transferring binary information between a central unit and a plurality of modular peripheral assemblies via a bus system wherein the bus system comprises a serial ring and further having an interface unit comprising a shift register of said serial ring associated with each peripheral assembly which permits parallel transfer of the binary information between each peripheral assembly and the bus system, each said interface unit being disposed in the serial ring and having a serial input and serial output connected in the serial ring and parallel outputs and inputs coupled to a respective peripheral assembly, said bus system further comprising a plurality of control lines for controlling said interface units, wherein the central unit makes information serially transferred via the bus system available to the interface units from a loading memory and further having a further memory wherein state data of the peripheral assemblies is loaded simultaneously, program processing taking place subsequently, the binary information being transferred from the peripheral assemblies before and after the serial transfer.

20. The method recited in claim 19, wherein, prior to the transfer of the binary information, at least one integral multiple of the binary information is loaded into the system as a preamble which is checked by the central unit after the completion of a selected number of counted register steps.

21. The method recited in claim 20, wherein said binary information comprises five bits.

22. A method for bidirectional information transfer on a line wherein a shift register cell of a serial ring shift register is coupled to an intermediate memory and an output of the memory is coupled to an input of a tristate amplifier, with an output of the tristate amplifier being coupled back to the shift register cell by a read amplifier comprising switching the tristate amplifier to its tristate condition when a control signal is supplied to the tristate amplifier and activating said read amplifier.