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Vertical type MOS transistor and method of formation thereof

  • US 4,845,537 A
  • Filed: 12/01/1987
  • Issued: 07/04/1989
  • Est. Priority Date: 12/01/1986
  • Status: Expired due to Fees
First Claim
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1. A vertical type MOS transistor comprising:

  • (a) a semiconductor substrate (21);

    (b) a first source-drain region (22) of a first conductivity type and formed selectively in a major surface of said semiconductor substrate;

    (c) an insulating layer (23) formed on the major surface of said semiconductor substrate;

    (d) said first source-drain region and said insulating layer having a trench (20) formed therethrough, said trench extending from a major surface of said insulating layer into a major surface of said first source-drain region, said trench having side walls and a bottom;

    (e) a second semiconductor layer (24) formed along said side walls and said bottom of said trench, a portion of said second semiconductor layer at least along said side wall being of a second conductivity type, different from said first conductivity type;

    (f) a third semiconductor layer (25) of said first conductivity type formed continuously from an upper end of said second semiconductor layer on the major surface of said insulating layer;

    (g) said transistor including a second source-drain region (25a), said semiconductor substrate and said third semiconductor layer being separated by said insulating layer, and said first and second source-drain regions being separated by said second semiconductor layer, wherein a channel length of said transistor is determined by a thickness of said insulating layer, independent of a depth of said trench;

    (h) a gate insulator (26) formed on the surface of said second semiconductor layer and the third semiconductor layer and in said trench; and

    (i) a gate electrode (27) formed on said gate insulator disposed in at least said trench.

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