Vertical type MOS transistor and method of formation thereof

• US 4,845,537 A
• Filed: 12/01/1987
• Issued: 07/04/1989
• Est. Priority Date: 12/01/1986
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ohsaki, Akihiko, Kusunoki, Shigeru, Sugahara, Kazuyuki, Nishimura, Tadashi
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Shingleton, Michael B.
• Application Number:
  US07/127,138
• Time in Patent Office: 581 Days
• Field of Search: 357/59 E, 357/23.6, 357/23.4, 357/41, 357/45, 357/51, 357/56
• US Class Current: 257/302
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs. 0O048455372

Claims

1. A vertical type MOS transistor comprising:

(a) a semiconductor substrate (21);

(b) a first source-drain region (22) of a first conductivity type and formed selectively in a major surface of said semiconductor substrate;

(c) an insulating layer (23) formed on the major surface of said semiconductor substrate;

(d) said first source-drain region and said insulating layer having a trench (20) formed therethrough, said trench extending from a major surface of said insulating layer into a major surface of said first source-drain region, said trench having side walls and a bottom;

(e) a second semiconductor layer (24) formed along said side walls and said bottom of said trench, a portion of said second semiconductor layer at least along said side wall being of a second conductivity type, different from said first conductivity type;

(f) a third semiconductor layer (25) of said first conductivity type formed continuously from an upper end of said second semiconductor layer on the major surface of said insulating layer;

(g) said transistor including a second source-drain region (25a), said semiconductor substrate and said third semiconductor layer being separated by said insulating layer, and said first and second source-drain regions being separated by said second semiconductor layer, wherein a channel length of said transistor is determined by a thickness of said insulating layer, independent of a depth of said trench;

(h) a gate insulator (26) formed on the surface of said second semiconductor layer and the third semiconductor layer and in said trench; and

(i) a gate electrode (27) formed on said gate insulator disposed in at least said trench.

2. A vertical type MOS transistor according to claim 1, wherein said gate electrode comprises a polycrystalline semiconductor.

3. A vertical type MOS transistor according to claim 1, wherein said gate electrode comprises silicide.

4. A vertical type MOS transistor according to claim 1, wherein said second semiconductor layer comprises monocrystalline silicon.

5. A vertical type MOS transistor according to claim 1, wherein said side walls of said trench form an angle of 60°

to 90°

with the major surface of said semiconductor substrate.

6. A vertical type MOS transistor according to claim 1, wherein said trench extends halfway through said first region.

7. A cross-point cell having one vertical type MOS transistor and one storage means disposed under said transistor, said cell comprising:

(a) a semiconductor substrate (21) of a first conductivity type;

(b) a first source-drain region (22) of a second conductivity type, different from said first conductivity type, and formed selectively in a major surface of said semiconductor substrate;

(c) an insulating layer (23) formed on the major surface of said substrate;

(d) a second semiconductor layer (24) formed along side walls and a bottom of a trench (20) which extends from a major surface of said insulating layer into the major surface of said substrate, a portion of said second layer at least on said side wall being of said first conductivity type;

(e) a third semiconductor layer (25) of said second conductivity type formed continuously from an upper end of said said second layer on the major surface of said insulating layer

(f) said third layer including a second source-drain region (25a) of said transistor, said semiconductor substrate and said third semiconductor layer being separated by said insulating layer, said first and second source-drain regions being separated by said second semiconductor layer, wherein a channel length of said transistor is defined by a thickness of said insulating layer, independent of a depth of said trench;

(g) a gate insulator (26) formed on the surface of said second layer and the third layer at least within said trench;

(h) a gate electrode (27) of said transistor formed on said gate insulator, and disposed in at least said trench;

(i) a first electrode (17) of said storage means formed just under said first source-drain region in said substrate and being of said second conductivity type; and

(j) a storage dielectric layer (16) formed between said substrate and said first electrode.