Scrolling image memory for high speed avionics moving map display
First Claim
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1. An image memory for avionics moving map displays, of the type having a system CPU, a mass storage device, and an image processor;
- the memory comprising;
a. a plurality of cells, each operatively coupled with the system CPU, the mass storage device and the image processor, and each cell being individually addressable and either receiving or outputting data irrespective of whether, simultaneously, any other cell is either outputting or receiving data;
b. a first portion of said plurality of cells for receiving input of data from the system CPU and the mass storage device;
c. a second portion of said plurality of cells for outputting data for scanning by the image processor.
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Abstract
A multichannel moving map display for high speed aircraft which utilizes a scrolling image memory which is arranged logically in an N+1×N+1 geometric array of memory cells and having an N×N active area for scanning by an image processor and a 2N+1 memory cell buffer area for loading updating information into the image memory and later redefining the active and buffer areas in order to allow for updating to occur.
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Citations
9 Claims
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1. An image memory for avionics moving map displays, of the type having a system CPU, a mass storage device, and an image processor;
- the memory comprising;
a. a plurality of cells, each operatively coupled with the system CPU, the mass storage device and the image processor, and each cell being individually addressable and either receiving or outputting data irrespective of whether, simultaneously, any other cell is either outputting or receiving data; b. a first portion of said plurality of cells for receiving input of data from the system CPU and the mass storage device; c. a second portion of said plurality of cells for outputting data for scanning by the image processor. - View Dependent Claims (2, 3, 4, 5)
- the memory comprising;
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6. A scrolling image memory for high speed avionics moving map displays comprising:
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a. a plurality of individually addressable cells, which are each simultaneously operable with any other cell of the plurality of cells; b. a data input into each of said plurality of cells; c. a data output from each of said plurality of cells; d. a write enable switch for each of said plurality of cells. e. a chip select switch for each of said plurality of cells; f. an active area address for each of said plurality of cells; g. a buffer area address for each of said plurality of cells; and h. an address select for each of said plurality of cells. - View Dependent Claims (7, 8, 9)
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Specification