On-chip bit reordering structure
First Claim
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1. A random access memory chip, comprising:
- a chip memory organized to hold a plurality of separate blocks of data, with each of said data blocks containing M individual data units in contiguous groups of N data units, where M is greater than N, and N is greater than one, with each data unit having its own unique address within said blocks, said memory having a predetermined wrap protocol, wherein said wrap protocol is a prescribed order for calling for all of said M data units in a given data block starting with a designated target data unit address and proceeding in said prescribed order, wherein a data unit at the end of a data block is contiguous in said prescribed order with a data unit at the beginning of said data block so that said beginning data unit follows said end data unit in said data block;
means for randomly addressing a data unit within a given block of data by means of a designated target address;
an N data unit chip output parallel interface from said memory;
chip register means for holding a given block of data, said chip register means having at least M register stages for holding said M data units of said given data block, wherein said M register stages are grouped into at least a first and a second contiguous groups of N stages each, said chip register means including first gating means for gating said first stage group of N register stages to said N data unit output parallel interface, followed in sequence, by said second stage group and higher groups; and
chip steering means for providing in a first set, and in any desired order, the data unit at said target address along with N-1 data units having following contiguous addresses for said memory wrap protocol from within said data block to said first group of N register stages, and for providing each successive set of N data units with following contiguous addresses in said wrap protocol to said second and higher register stage groups, wherein the data unit, if any, following the end data unit in the data block is always the beginning data unit in the data block.
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Abstract
An apparatus and method whereby a static column mode DRAM can access a unique data bit located anywhere within the array chip and sustain a continuous transfer of requested bits in a contiguous group of bits (i.e. block). Steering of the data in a prescribed order is accomplished via a special steering and gating network. A control line, toggle, is used on both rising and falling edges to produce this gapless transfer.
179 Citations
31 Claims
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1. A random access memory chip, comprising:
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a chip memory organized to hold a plurality of separate blocks of data, with each of said data blocks containing M individual data units in contiguous groups of N data units, where M is greater than N, and N is greater than one, with each data unit having its own unique address within said blocks, said memory having a predetermined wrap protocol, wherein said wrap protocol is a prescribed order for calling for all of said M data units in a given data block starting with a designated target data unit address and proceeding in said prescribed order, wherein a data unit at the end of a data block is contiguous in said prescribed order with a data unit at the beginning of said data block so that said beginning data unit follows said end data unit in said data block; means for randomly addressing a data unit within a given block of data by means of a designated target address; an N data unit chip output parallel interface from said memory; chip register means for holding a given block of data, said chip register means having at least M register stages for holding said M data units of said given data block, wherein said M register stages are grouped into at least a first and a second contiguous groups of N stages each, said chip register means including first gating means for gating said first stage group of N register stages to said N data unit output parallel interface, followed in sequence, by said second stage group and higher groups; and chip steering means for providing in a first set, and in any desired order, the data unit at said target address along with N-1 data units having following contiguous addresses for said memory wrap protocol from within said data block to said first group of N register stages, and for providing each successive set of N data units with following contiguous addresses in said wrap protocol to said second and higher register stage groups, wherein the data unit, if any, following the end data unit in the data block is always the beginning data unit in the data block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 30)
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14. A method for transferring a block of data held within a random access memory chip to an N data unit output parallel interface, said memory being organized to hold a plurality of said blocks of data, with each of said blocks containing M individual data units in an initial data unit order and in contiguous groups of N data units, where M is greater than N and N is greater than one, with each data unit having its own unique address within said block, said memory having a predetermined wrap protocol, wherein said wrap protocol is a prescribed order calling for said M data units in a given data block starting with a designated target data unit address and proceeding in said prescribed order, wherein a data unit at the end of a data block is contiguous in said prescribed order with a data unit at the beginning of said data block so that said beginning data unit follows said end data unit, comprising the internal chip operations of:
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randomly addressing a data unit within a given block of data held in a memory chip by means of a designated target address; holding said data block in its initial data unit order within said memory chip; reordering said data unit order within said memory chip so that the data unit with the target address along with the N-1 data units having following contiguous addresses in said memory wrap protocol are held in any order in the first N positions in said data unit order, and reordering so that each successive set of N data units with following contiguous addresses in said wrap protocol is held in the second and higher N position groups in the order, respectively wherein the data unit, if any, following the end data unit in the data block is always the beginning data unit in the data block; and gating said first N positions in said reordered data unit order in said chip memory to said N data unit chip output parallel interface, followed, in sequence, by said second N position group and higher N position groups. - View Dependent Claims (15, 16, 17, 18)
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19. A random access memory chip, comprising:
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a chip memory organized to hold a plurality of separate blocks of data, with each of said data blocks containing M individual data buts in an initial order in contiguous groups of N bits, where M is greater than N, and N is greater than one, with each data unit having its own unique address within said block, said memory having a predetermined wrap protocol wherein said wrap protocol is a prescribed order calling for said M bits to be accessed starting with a target bit address and proceeding in said prescribed order, wherein a bit at the end of a data block is contiguous in said prescribed order with a bit at the beginning of said data block so that said beginning bit follows said end bit in said data block; chip address means for randomly addressing a data bit in a given block of data held in said chip memory by means of a target address; an N bit chip output parallel interface from said chip memory; means for holding said given data block in its initial data bit order within said chip; means for reordering said data bit order into a reordered data bit order so that the bit with the target address along with N-1 bits having following contiguous addresses in said memory wrap protocol are held in any order in the first N positions in said reordered data bit order, and reordering so that each successive set of N bits with following contiguous addresses in said wrap protocol is held in second and higher N position groups, respectively, within said reordered data bit order, wherein the bit, if any, following the end bit in the data block is always the beginning bit in the data block; and first chip gating means for gating said first N positions in said reordered data bit order to said N bit chip output parallel interface, followed, in sequence, by said second N positions and higher N position groups. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31)
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Specification