Method and apparatus for data exchange between microprocessors

• US 4,845,667 A
• Filed: 09/22/1988
• Issued: 07/04/1989
• Est. Priority Date: 01/16/1985
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Perenthaler, Egbert, van Woudenberg, Jan F., Zucker, Udo, Lotterbach, Gerhard, Hoptner, Wolfgang
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/249,267
• Time in Patent Office: 285 Days
• Field of Search: 370/60, 370/94, 370/85, 370/89, 370/100, 364/200 MS File, 364/900 MS File, 364/424, 364/426, 379/88, 379/196, 379/211
• US Class Current: 701/102
• CPC Class Codes: F02D 41/266 the computer being backed-up or assisted by another circuit, e.g. analogue
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A method and apparatus for data exchange between a master microprocessor and a slave microprocessor, in which the connection is a parallel bus and the data exchange requires a minimum of time. For this purpose, the data are transmitted in a predetermined sequence and in which the transmission-start identifier is a signal train generated by the master processor which is specifically associated with data transmission. Preferably, a master processor and a slave processor are interconnected by the parallel data bus, with buffer memories, such as latches, interposed. A toggle flip-flop is connected to the interrupt input of the slave processor in such a way that merely placing a specific instruction (i.e. command+data) on the bus simultaneously notifies the slave processor to prepare for the exchange of data, thereby saving time.

Claims

1. A method of exchanging data in a control system of an automotive vehicle between a master processor (10) and a slave processor (12) of said control system with a minimum of extra data transmitted and time consumed,

comprising the steps of

generating a synchronous timing reference for both said master processor (10) and said slave processor (12);

generating in said master processor a signal train in form of write or read commands, followed by said data, wherein the data are provided in form of data words, in a predetermined pattern and sequence;

loading the write or read command and the data in said sequence into a first latch (11);

recognizing, in the latch, the presence of the write or read command;

transmitting to said first latch, a second time, the write or read command;

toggling a two-command recognition circuit (15) or register in dependence on recognition of the second write or read command;

generating an interrupt signal (40) upon such recognition of two commands, and coupling said interrupt signal to an interrupt input of said slave processor (12) to thereby initialize (31,

     32), said slave processor for the reception of a first data word;

transferring (33) said first data word from said first intermediate latch (11) into said slave processor (12);

signalling (P,

     35) by said slave processor said master processor (10) that said slave processor (12) has received the first data word;

generating a single write or read command to thereby provide a command to the recognition circuit or register (15) and thereby changing the status of the interrupt line of said slave processor to initialize said slave processor for the reception of a further data word;

transferring (23) said further data word to said slave processor (12) and

completing said data transmission by setting said recognition circuit (15) or register to the status before said first pair of write or read commands.

2. The method according to claim 1, including the steps of signalling (P, 35) said master processor (10) each time said slave processor (12) has received a data word, and further signalling the master processor that the slave processor has received the final data word of the transmission.

3. The method according to claim 2, wherein the end of the transmission is signalled by alternate read and write commands.

4. The method according to claim 1, further comprising the step of (FIG. 3) counting, in said slave processor (12) the number of switch-over or interrupt signals received after the first interrupt signal.

5. The method according to claim 1, further comprising the step of returning (36) said slave processor (12) to execution of a slave program after said exchange of data, which slave program the slave processor executing prior to said data exchange.

6. The method according to claim 1, including the step of generating, in the slave processor, a write command and data in form of at least one data word;

loading the write command and said at least one data word from the slave processor (12) into a second latch (13);

generating, in the master processor (10), an interrogation signal and coupling said interrogation signal to the slave processor (12) to determine if the slave processor has received said data and, selectively, read data into said second latch, said interrogation signal including the first recognition command to the recognition circuit or register (15).

7. The method according to claim 6, wherein said first recognition command comprises a "read" command directed by said master processor (10) to said second latch (13), and including the step of reading said at least one data word from the second latch into the master processor (10).

8. The method according to claim 1, wherein said data words comprise control data for different operating parameters of an engine of the vehicle.

9. The method according to claim 1, wherein at least one of said data words represents data controlling injection of fuel to an internal combustion engine of the vehicle.

10. The method according to claim 1, wherein the step of recognizing the presence of the first write or read command and the step of recognizing the second write or read command comprises recognizing respectively opposite flanks or edges of a pulse (40).

11. System for exchanging of data in a control system of an internal combustion engine, between a master processor (10) and a slave processor (12), said data comprising data trains in form of write or read commands, followed by data words in a predetermined time or sequence,

wherein said slave processor (12) has an INTERRUPT input;

the master processor has an input/output port for transmitting and receiving said data trains, respectively;

said slave processor (12) has an input/output port for receiving and transmitting the data trains, respectively;

and at least one latch (12) is provided, forming a buffer memory, coupled between the input/output ports of the master processor and the slave processor, and a recognition circuit or register (15) is provided, connected to and responsive to two commands in said data trains, and forming at least one of;

write commands;

read commands, and means for controlling the INTERRUPT input of said slave processor (12) to interrupt processing operation by the slave processor when two commands are received and recognized by said recognition circuit or register (15).

12. The system according to claim 11, including resetting means (16) coupled to the master processor (10) and said recognition circuit or register (15) for placing said recognition circuit or register in a predetermined condition upon control by said master processor.

13. The system according to claim 11, further including a check line connection (P-R) to permit signalling between the slave processor (12) and the master processor (10) that a data word has been read into the slave processor from said at least one latch.

14. The system according to claim 11, further including a second latch (13) coupled to receive transmitted data from said slave processor and further coupled to said master processor (10) to permit reading of data from the slave processor into the second latch, and read-out of data from said second latch into the master processor, said data being preceded by respective "read" commands from the master processor upon read-out by the master processor, said command forming one of the respective commands controlling the INTERRUPT input from the recognition circuit or register (15).

15. A method of exchanging data in a control system of an automotive vehicle between a master processor (10) and a slave processor (12) of said control system with a minimum of extra data transmitted and time consumed,

comprising the steps of

generating in said master processor (10) a signal train in form of a pair of write commands followed by data words in a predetermined patter and sequence;

loading the write commands and the data of said data words in said sequence into a latch (11);

recognizing presence of the two write commands;

toggling a recognition circuit or register (15) in dependence on recognition of the second write command;

generating, upon such recognition, an interrupt signal (40) and coupling said interrupt signal to an INTERRUPT input of said slave processor (12) to thereby initialize (31,

     32) said slave processor for the reception of a first data word;

transferring said first data word from said latch (11) into said slave processor (12);

signalling (P,

     32) to said master processor (11) that said slave processor has received the first data word;

changing the status of the interrupt line by a single write command;

transferring further data words to said slave processor including pairs of write commands; and

completing said data transmission by setting said recognition circuit or register (15) to a rest status thereof and ready to receive a further pair of write commands.

16. The method according to claim 15 wherein said signalling step from the slave processor (12) to the master processor (10) that the slave processor has received the first data word forms one of the pairs of commands for said two-command recognition or register circuit (15).