Memory device using shift-register
First Claim
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1. A memory device comprising:
- a least one memory array;
at least one input-output circuit for transmitting a pair of input signals having mutually opposite phases;
at least one clock generating circuit for generating a plurality of clock pulses;
at least one shift register having a plurality of series connected stages, each of said stages having a dynamic comparator circuit comprising first and second transistor groups, said first and second transistor groups being controlled by said pair of input signals respectively and cooperating with each other under the control of said clock pulses so that a first node potential corresponding to said first transistor group makes a second node potential corresponding to said second transistor group rise, and said second node potential makes said first node potential drop, such that third and fourth node potentials corresponding to said first and second nodes respectively are fixed as a pair of fixed voltage signals, and each of said stages having a buffer circuit for receiving said pair of fixed voltage signals and for making an impedance condition change from a high impedance condition to a low impedance condition;
a plurality of switching circuits for controlling signal transfer between each of said stages of said shift register and said at least one memory array by means of said clock pulses.
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Abstract
In a memory device, a shift-register comprises a plurality of stages for transferring sequentially a pair of signals which have mutually opposite phases. Each stage has a comparator circuit which compares the pair of signals and generates a pair of fixed voltage signals. By this construction, high-speed operation of the memory device, low power consumptions, and high-capacity load driving are achieved.
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Citations
10 Claims
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1. A memory device comprising:
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a least one memory array; at least one input-output circuit for transmitting a pair of input signals having mutually opposite phases; at least one clock generating circuit for generating a plurality of clock pulses; at least one shift register having a plurality of series connected stages, each of said stages having a dynamic comparator circuit comprising first and second transistor groups, said first and second transistor groups being controlled by said pair of input signals respectively and cooperating with each other under the control of said clock pulses so that a first node potential corresponding to said first transistor group makes a second node potential corresponding to said second transistor group rise, and said second node potential makes said first node potential drop, such that third and fourth node potentials corresponding to said first and second nodes respectively are fixed as a pair of fixed voltage signals, and each of said stages having a buffer circuit for receiving said pair of fixed voltage signals and for making an impedance condition change from a high impedance condition to a low impedance condition; a plurality of switching circuits for controlling signal transfer between each of said stages of said shift register and said at least one memory array by means of said clock pulses. - View Dependent Claims (2, 3)
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4. A shift register comprising:
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a plurality of stages for transferring a pair of signals having mutual opposite phases, each of said stages comprising; two input terminals to which said pair of signals are transmitted; a dynamic comparator circuit comprising first and second transistor groups, said first and second transistor groups being respectively controlled by said pair of input signals and cooperating with each other under the control of said clock pulses so that a first node potential corresponding to said first transistor group makes a second node potential corresponding to said second transistor group rise, and said second node potential makes said first node potential drop, such that third and fourth node potentials corresponding to said first and second nodes respectively are fixed as a pair of fixed voltage signals, a buffer circuit for receiving said pair of fixed voltage signals and for changing an impedance condition from a high impedance condition to a low impedance condition, two output terminals responsive to said dynamic comparator circuit for transmitting said pair of fixed voltage signals to a succeeding stage. - View Dependent Claims (5, 6, 7, 8)
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9. An electronic circuit comprising:
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a dynamic comparator circuit comprised of first and second transistor groups, said first and second transistor groups being controlled by a pair of input signals respectively having mutually opposite phases and cooperating with each other under the control of clock pulses so that a first node potential corresponding to said first transistor group makes a second node potential corresponding to said second transistor group rise, and so that said second node potential makes said first node potential drop, and thereby third and fourth node potentials corresponding to said first and second nodes respectively are fixed as a pair of fixed voltage signals; a buffer circuit for receiving said pair of fixed voltage signals and for changing an impedance condition from a high impedance condition to a low impedance condition; and
,a latch circuit for holding said pair of fixed voltage signals by means of at least one pair of cooperating transistors. - View Dependent Claims (10)
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Specification