Pipelined memory chip structure having improved cycle time
First Claim
1. A piplined semiconductor 2n Kbit memory chip, n being an integer not less than 2, said chip being segmented into a plurality of 2n-y memory sub-arrays of 2y Kbits arranged in columns and rows on said chip, each one of said 2n-y memory sub-arrays includes a separate associated word line driver circuit means, sense amplifier circuit means and independent precharge circuit means connected thereto, each of said independent precharge circuit means of each of said segmented memory sub-arrays providing local self-timed reset and precharge function for each segmented memory array independent of said other of said plurality of 2n-y memory arrays,wherein said memory chip exhibits an access time t for providing data from said memory chip and wherein said local reset and precharge circuits of each of said segmented memory sub-arrays provides a cycle time for each sub-array which is less than chip access time t.
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Accused Products
Abstract
A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding and precharging. The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.
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Citations
5 Claims
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1. A piplined semiconductor 2n Kbit memory chip, n being an integer not less than 2, said chip being segmented into a plurality of 2n-y memory sub-arrays of 2y Kbits arranged in columns and rows on said chip, each one of said 2n-y memory sub-arrays includes a separate associated word line driver circuit means, sense amplifier circuit means and independent precharge circuit means connected thereto, each of said independent precharge circuit means of each of said segmented memory sub-arrays providing local self-timed reset and precharge function for each segmented memory array independent of said other of said plurality of 2n-y memory arrays,
wherein said memory chip exhibits an access time t for providing data from said memory chip and wherein said local reset and precharge circuits of each of said segmented memory sub-arrays provides a cycle time for each sub-array which is less than chip access time t.
Specification