Nonvolatile semiconductor memory device

• US 4,845,680 A
• Filed: 07/06/1988
• Issued: 07/04/1989
• Est. Priority Date: 12/27/1985
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwahashi, Hiroshi
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US07/218,490
• Time in Patent Office: 363 Days
• Field of Search: 365/185, 365/230
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors

Abstract

A nonvolatile memory device includes first and second voltage lines whose potentials are selectively set, first and second gate control lines, first to third MOS transistors which are serially connected between the first and second voltage lines, the first and third MOS transistors having gates respectively connnected to the first and second gate control lines and the second MOS transistor having a gate set in an electrically floating conditions, first and second capacitors respectively connected between the gate of the second MOS transistor and the gates of the first and third MOS transistors, and third capacitor connected between the gate and drain of the second MOS transistor.

Claims

1. A nonvolatile memory device comprising:

row decoding means;

first and second column decoding means;

M row lines connected to said row decoding means;

N column selection lines connected to said first column decoding means;

N column control lines connected to said second column decoding means;

N data transfer lines;

a source line;

N memory blocks each including n column lines, n switching means which are respectively connected between said n data transfer lines and said n column lines and whose control terminals are commonly connected to a corresponding one of said N column selection lines, M gate control lines, M second switching circuits which are respectively connected between a corresponding one of said N column control lines and said M gate control lines and whose control terminals are respectively connected to said M row lines, n series circuit which are respectively connected between said source line and said n column lines and each of which includes first MOS transistor having a gate connected to the corresponding one of said column control lines and a second MOS transistor serially connected with said first MOS transistor and having a gate connected to receive a control signal, and memory cells arranged in a matrix form, those of said memory cells which lie on the same row being connected to a corresponding one of said M row lines and to a corresponding one of said M gate control lines, and those of said memory cells which lie on the same column being connected to a corresponding one of said n column lines, and each of said memory cells including,

first, second and third MOS transistors which are serially connected between the corresponding one of said column lines and said source line, said first and third MOS transistors having gates respectively connected to the corresponding one of said row lines and the corresponding one of said gate control lines and said second MOS transistor having a gate set in

an electrically floating condition, first and second capacitive means respectively connected between the gate of said second MOS transistor and the gates of said first and third MOS transistors, and

third capacitive means connected between the gate and drain of said second MOS transistor.

2. A memory device according to claim 1, wherein said row line and the gate of said first MOS transistor are formed of a first conductive layer, the gate of said second MOS transistor is formed of a second conductive layer, and said gate control line and the gate of said third MOS transistor are formed of a third conductive layer.

3. A memory device according to claim 2, wherein said first and second conductive layers have overlapping portions which constitute said first capacitive means, and said second and third conductive layers have overlapping portions constitute said second capacitive means.

4. A memory device according to claim 3, wherein a source region of said first MOS transistor and a drain region of said second MOS transistor are formed of the same semiconductor region, and said second conductive layer is formed to overlap said semiconductor region, constituting said third capacitive means.

5. A memory device according to claim 4, wherein each of said first, second and third conductive layers is formed of polycrystalline silicon.

6. A memory device according to claim 2, wherein each of said first, second and third conductive layers is formed of polycrystalline silicon.

7. A memory device according to claim 2, wherein said second conductive layer has a portion disposed between said first and third conductive layers.

8. A nonvolatile memory device comprising:

first and second voltage lines each having a selectively set potential;

first and second gate control lines;

first, second and third MOS transistors serially connected between said first and second voltage lines, said first and third MOS transistors each having gates respectively connected to said first and second gate control lines and said second MOS transistor having a gate set in an electrically floating condition;

first and second capacitive means respectively connected between the gate of said second MOS transistor and the gates of said first and third MOS transistors; and

third capacitive means connected between the gate and drain of said second MOS transistor;

wherein said first gate control line and the gate of said first MOS transistor are formed of a first conductive layer (47), the gate of said second MOS transistor is formed of a second conductive layer (51) and said second gate control line and the gate of said third MOS transistor are formed of a third conductive layer (49);

and wherein said first conductive layer (47) includes at least one projection portion (47A) overlapping a part of said second conductive layer (51) to form said first capacitive means (64), and said third conductive layer (49) includes at least one step portion (49A) extending below a part of said second conductive layer (51) to form said second capacitive means (65).

9. A nonvolatile memory device according to claim 8, wherein a source region of said first MOS transistor and a rain region of said second MOS transistor are formed of the same semiconductor region, said second conductive layer overlapping said semiconductor region to form said third capacitive means (66).

10. A nonvolatile memory device according to claim 9, wherein each of said first, second, and third conductive layers is formed of polycrystalline silicon.

11. A nonvolatile memory device according to claim 8, wherein said second conductive layer (51) includes a first pair of oppositely facing side edges and a second pair of side edges substantially perpendicular to said first pair of side edges;

wherein said third conductive layer (49) has a U-shape with two parallel conductive lines surrounding said second conductive layer (51);

wherein said third conductive layer (49) includes first and second step portions (49A) extending below a part of said second conductive layer (51); and

wherein said first conductive layer (47) is formed in a direction substantially perpendicular to the two parallel conductive lines of said third conductive layer (49).

12. A nonvolatile memory device comprising:

first and second voltage lines each having a selectively set potential;

first and second gate control lines;

first, second and third MOS transistors serially connected between said first and second voltage lines, said first and third MOS transistors each having gates respectively connected to said first and second gate control lines and said second MOS transistor having a gate set in an electrically floating condition;

first and second capacitive means respectively connected between the gate of said second MOS transistor and the gates of said first and third MOS transistors; and

third capacitive means connected between the gate and drain of said second MOS transistor;

wherein said first gate control line and the gate of said first MOS transistor are formed of a first conductive layer (47), the gate of said second MOS transistor is formed of a second conductive layer (51) and said second gate control line and the gate of said third MOS transistor are formed of a third conductive layer (49);

and wherein said first and third conductive layers (47,

     49) overlap at a crossing point and said second conductive layer (51) has a projection portion (51A) arranged between the first and third conductive layers (47,

     49) at said crossing point to form said first and third capacitive means (64,

     66).

13. A nonvolatile memory device according to claim 12 wherein a source region of said first MOS transistor and a drain region of said second MOS transistor are formed in the same semiconductor region, said second conductive layer overlapping said semiconductor region to form said third capacitive means.

14. A nonvolatile memory device according to claim 12, wherein each of said first, second, and third conductive layers is formed of polycrystalline silicon.