Security and alarm system employing a particular pulse width discriminator
First Claim
1. A pulse width discriminator circuit, comprising:
- a D-type flip-flop having a data input, a clock input, a data output, and an inverted data output;
a retriggerable monostable multivibrator having a trigger input, an external capacitance input, an external resistance-capacitance input, and an inverted data output;
a capacitor; and
first and second resistors;
wherein said first resistor has one end connected to a source of power and its other end connected to said external resistance-capacitance input of said monostable multivibrator;
wherein said capacitor has one end connected to said external capacitance input of said monostable multivibrator, and its other end connected to said external resistance-capacitance input of said monostable multivibrator, wherein said second resistor has one end connected to said data output of said flip-flop and its other end connected to said external resistance-capacitance input of said monostable multivibrator; and
wherein when an input signal which is approximately a square wave is applied to said trigger input of said monostable multivibrator and to said data input of said flip-flop, said flip-flop produces at said inverted data output thereof an output signal which is a logic high voltage when the frequency of said input signal has exceede a fist predetermined frequency and until the frequency of said input signal thereafter falls below a second predetermined frequency which is less than said first predetermined frequency, and which is a logic low voltage when said input signal has fallen below said second predetermined frequency and until said input signal again exceeds said first predetermined frequency.
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Abstract
A security and alarm apparatus has a pulse width discriminator circuit which includes: a monostable multivibrator having a trigger input connected to a data input of a flip-flop, a data output connected to a clock input of the flip-flop, and a pulse width control input; and a pulse width control circuit connected to the pulse width control input which causes a pulse produced by the monostable multivibrator to have one width when the flip-flop is in a first state and a larger width when the flip-flop is in a second state, the flip-flop producing at its data output a signal which is a logic high voltage when the frequency of an input signal at the trigger input has exceeded a first predetermined frequency and until it thereafter falls below a second predetermined frequency less than said first predetermined frequency, and which is a logic low voltage when the input signal has fallen below the second predetermined frequency until the input signal again exceeds the first predetermined frequency. The apparatus includes a plurality of sensors which can each detect an alarm condition, a radio transmitter which transmits a detected alarm condition to a radio receiver having an output connected to the trigger input, and an arrangement producing a display in response to the output of the flip-flop.
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Citations
6 Claims
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1. A pulse width discriminator circuit, comprising:
- a D-type flip-flop having a data input, a clock input, a data output, and an inverted data output;
a retriggerable monostable multivibrator having a trigger input, an external capacitance input, an external resistance-capacitance input, and an inverted data output;
a capacitor; and
first and second resistors;
wherein said first resistor has one end connected to a source of power and its other end connected to said external resistance-capacitance input of said monostable multivibrator;
wherein said capacitor has one end connected to said external capacitance input of said monostable multivibrator, and its other end connected to said external resistance-capacitance input of said monostable multivibrator, wherein said second resistor has one end connected to said data output of said flip-flop and its other end connected to said external resistance-capacitance input of said monostable multivibrator; and
wherein when an input signal which is approximately a square wave is applied to said trigger input of said monostable multivibrator and to said data input of said flip-flop, said flip-flop produces at said inverted data output thereof an output signal which is a logic high voltage when the frequency of said input signal has exceede a fist predetermined frequency and until the frequency of said input signal thereafter falls below a second predetermined frequency which is less than said first predetermined frequency, and which is a logic low voltage when said input signal has fallen below said second predetermined frequency and until said input signal again exceeds said first predetermined frequency.
- a D-type flip-flop having a data input, a clock input, a data output, and an inverted data output;
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2. A circuit having a pulse width discriminator, comprising:
- a D-type flip-flop having a data input, a clock input, and a data output;
a monostable multivibrator having a trigger input which is connected to said data input of said flip-flop, a data output which is connected to said clock input of said flip-flop, and a pulse width control input; and
pulse width control circuit means connected to said pulse width control input of said monostable multivibrator for determining the width of a pulse produced by said monostable multivibrator when an input signal applied to said trigger input actuates said monostable multivibrator, said clock input of said flip-flop being responsive to the trailing edge of each pulse from said monostable multivibrator, said pulse width control circuit means including hysteresis circuit means for causing a pulse produced by said monostable multivibrator to have a first width when said flip-flop is in a first state and to have a second width slightly greater than said first width when said flip-flop is in a second state;
wherein when an AC input signal is applied to said trigger input of said monostable multivibrator, said flip-flop produces at said data output thereof an output signal which is a logic high voltage when the frequency of said input signal has exceeded a first predetermined frequency and until the frequency of said input signal thereafter falls below a second predetermined frequency which is less than said first predetermined frequency, and which is a logic low voltage when said input signal has fallen below said second predetermined frequency until said input signal again exceeds said first predetermined frequency. - View Dependent Claims (3, 4, 5, 6)
- a D-type flip-flop having a data input, a clock input, and a data output;
Specification