Data transmission system for a computer controlled copying machine having master and slave CPU's

• US 4,847,756 A
• Filed: 06/12/1987
• Issued: 07/11/1989
• Est. Priority Date: 01/11/1983
• Status: Expired due to Fees

• Current Assignee: Minolta Camera Kabushiki Kaisha
• Original Assignee: Minolta Camera Kabushiki Kaisha
• Inventors: Ito, Masazumi, Shibazaki, Kenji
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Munteanu, Florin
• Application Number:
  US07/062,562
• Time in Patent Office: 760 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/131, 364/132, 355/14 C, 370/85, 370/94, 370/95, 340/825.06, 340/825.07, 340/825.08
• US Class Current: 709/208
• CPC Class Codes: G03G 15/50 Machine control of apparatus for electrographic processes using a charge pattern, e.g. regulating differents parts of the machine, multimode copiers, microprocessor control sequencing control G03G21/14
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A data transmission system includes a host CPU having an output terminal for repeatedly producing a predetermined number of data blocks in a predetermined sequence in a repeated manner. Each data block is defined by a sequence code for identifying each data block and specific data followed by the sequence code. A plurality of slave CPUs are provided. The host CPU is connected to each slave CPU through a bus structure for the mutual data transmission. Each slave CPU receives all the data blocks and selectively extracts only the necessary data for use in each slave CPU and produces data from its output terminal at a given period within one cycle of the predetermined sequence. The given period for one slave CPU differs from that of another slave CPU, thereby transmitting data to the host CPU without any interferences.

Claims

1. A data transmission system comprising:

a host CPU having an output terminal means for repeatedly producing first data in a predetermined sequence, and an input terminal means for receiving second data, wherein said first data comprises a predetermined number of data blocks produced in a predetermined sequence in a repeated manner, each data block including a sequence code, which is different from those in other data blocks, for identifying each data block and specific data;

a bus structure having at least one first-type of line extending from said output terminal means of said host CPU for transmitting said first data, and at least one second-type of line extending from said input terminal means of said host CPU for receiving said second data;

a plurality of slave CPU'"'"'s, each having at least one name code which corresponds to one of the sequence codes, each having an input terminal means connected to said first-type line of said bus structure for receiving said first data, and an output terminal means connected to said second-type line of said bus structure for sending said second data from said slave CPU;

means, in each slave CPU, for receiving the first data;

means, in each slave CPU, for detecting said sequence code defined in said first data;

means, in each slave CPU, for operating upon the data in the data block when the detecting means detects that the data block includes the sequence code that corresponds to the name code of the slave CPU;

means, in each slave CPU, for enabling said slave CPU to transmit data to said host CPU when said sequence code as detected by said detecting means indicates that, during the next successive data block, data is to be transmitted from said slave CPU to said host CPU at a predetermined sequence, that has been allotted to said slave CPU, and

means for sending data from said slave CPU to said host CPU during the next sequence of transmitting data from said host CPU to all of the slave CPU'"'"'s.

2. A data transmission system as claimed in claim 1, wherein said output terminal means of said host CPU comprises one terminal through which said data block is sent as a bit-by-bit serial data block, and wherein said input terminal means of each slave CPU comprises one terminal through which said serial data block is received bit-by-bit.

3. A data transmission system as claimed in claim 1, wherein said output terminal means of each slave CPU comprises one terminal through which said second data is sent as bit-by-bit serial data, and wherein said input terminal means of each host CPU comprises one terminal through which said serial second data is received bit-by-bit.

4. A data transmission system as claimed in claim 1, wherein said host CPU further has an interruption signal producing terminal for producing an interruption signal, said bus structure further having a third-type of line extending from said interruption signal producing terminal, and each slave CPU further having an interruption signal receiving terminal connected to said third-type of line for receiving said interruption signal, whereby the transmission of said first and second data is carried out during the presence of said interruption signal.

5. A data transmission system as claimed in claim 1, wherein said host CPU further has a clock pulse producing terminal for producing clock pulses, said bus structure further having a fourth-type of line extending from said clock pulse producing terminal, and each slave CPU further having a clock pulse receiving terminal connected to said fourth-type of line for receiving said clock pulses, whereby the transmission procedure is synchronized between said host CPU and each slave CPU.

6. The invention of claim 1 wherein the detecting means, in each slave CPU includes a shift register enabled to receive the data blocks of said first data.

7. In a computer controlled copying system for reproducing copies of indicia from originals having a master CPU and a plurality of slave CPU'"'"'s responsive to the master CPU for monitoring and/or controlling certain copying functions, the improvement comprising:

means for providing a clock terminal, a serial-in terminal and a serial-out terminal on the master CPU;

means for providing a clock terminal and a serial-in terminal on all of the slave CPU'"'"'s;

means for providing a serial-out terminal on some of the slave CPU'"'"'s;

a common data bus extending between the master CPU and each of the slave CPU'"'"'s, including a plurality of communication lines, a respective communication line connected to a terminal on the master CPU and to each of the appropriate terminals provided on the slave CPU'"'"'s;

means for generating timing pulses for transmission from the clock terminal of the master CPU to the clock terminals of the slave CPU'"'"'s to synchronize their respective operations;

means, in the master CPU, for forming and serially transmitting at a predetermined frequency, through the serial-out terminal of the master CPU, data blocks, each data block including a sequence code that identifies the type of data information carried by that data block;

means, in each slave CPU, for receiving each data block through its serial-in terminal including the sequence code and for determining if that data block should be processed by the slave CPU, and

means, in those slave CPU'"'"'s having a serial out terminal, for enabling, from evaluation of the sequence code, that slave CPU to transmit data to the master CPU in proper sequence, wherein the means for enabling includes a predetermined code stored in each slave CPU, means for calculating the next sequence code in order from the received sequence code and means for matching the calculated code with the predetermined code for that slave CPU, for determining the next data block to be transmitted by the master CPU, the enabling means permitting the slave CPU to transmit data to the master CPU during the sending of the next data block.

8. A computer controlled copying system as claimed in claim 7, further including an interruption signal means for producing an interrupt signal wherein an interrupt request terminal means on the master CPU and an interrupt request terminal on all slave CPUs are operatively connected through the common data bus whereby the transmission of data blocks from the master CPU to the slave CPUs and the transmission of data to the master CPU from those CPUs having a serial out terminal is carried out during the presence of the interrupt signal.

9. In a computer controlled copying system for reproducing copies of indicia from originals having a master CPU and a plurality of slave CPU'"'"'s responsive to the master CPU for monitoring and/or controlling certain copying functions, at least some of the slave CPU'"'"'s have a data transmitting capability, the improvement comprising:

a common data bus extending between the master CPU and each of the slave CPU'"'"'s;

means, in the master CPU, for forming and serially transmitting at a predetermined frequency data blocks on the data bus, each data block including a sequence code that identifies the type of data information carried by that data block;

means, in each slave CPU, for receiving each data block from the data bus, including the sequence code and for determining if that data block should be processed by the slave CPU, and

means, in those slave CPU'"'"'s having a data transmitting capability, for enabling, from evaluation of the sequence code, the slave CPU to transmit data to the master CPU in proper sequence, wherein the means for enabling includes a predetermined code stored in the slave CPU, means for calculating the next sequence code in order from the received sequence code and means for matching the calculated code with the predetermined code for the slave CPU for determining the next data block to be transmitted by the master CPU, the enabling means permitting the slave CPU to transmit data to the master CPU during the sending of the next data block.