Digital registers with serial accessed mode control bit
First Claim
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1. A reconfigurable digital register, comprising:
- a plurality of means for retaining an electrical signal indicative of either a first or a second state;
means for serially loading said plurality of means for retaining an electrical signal in response to a first control signal, so that said state is set for each of said plurality of means for retaining an electrical signal; and
an additional means for retaining an electrical signal indicative of either a first or a second state, wherein said additional means for retaining an electrical signal is capable of being serially loaded along with said plurality of means for retaining an electrical signal, and wherein said state of said additional means for retaining an electrical signal is indicative of two different modes of operation of said register.
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Abstract
A reconfigurable digital register that can be serially loaded has an additional bit associated with the register which holds information indicative of a mode of operation of the register. The mode control bit is located such that it can be serially loaded along with the other bits. A particularly useful embodiment is to use the mode control bit to configure the register as either a test pattern generator or a signature analysis register in support of integrated circuit self-test functions.
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Citations
15 Claims
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1. A reconfigurable digital register, comprising:
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a plurality of means for retaining an electrical signal indicative of either a first or a second state; means for serially loading said plurality of means for retaining an electrical signal in response to a first control signal, so that said state is set for each of said plurality of means for retaining an electrical signal; and an additional means for retaining an electrical signal indicative of either a first or a second state, wherein said additional means for retaining an electrical signal is capable of being serially loaded along with said plurality of means for retaining an electrical signal, and wherein said state of said additional means for retaining an electrical signal is indicative of two different modes of operation of said register. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An electronic apparatus for selectively configuring one or more digital registers to facilitate the testing of the response of a digital logic circuit to a plurality of digital test patterns, said digital logic circuit having an input and an output, said apparatus comprising:
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first digital register including a first set of bits; means for serially loading said first set of bits in response to a first control signal; and means for configuring said first digital register to automatically and sequentially generate said digital test patterns and apply, directly or indirectly, said test patterns individually to at least part of said digital logic circuit input, wherein said means for configuring said first digital register includes access lines to said first set of bits and an additional bit, wherein the state of said additional bit can be set so that when a second control signal is applied to said access lines to said first set of bits, the state of said additional bit will be determined and said test patterns will be generated, and wherein said means for configuring said first digital register also includes means for serially loading said additional bit along with said first set of bits. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A reconfigurable digital register, comprising:
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a plurality of means for retaining an electrical signal indicative of either a first or a second state, said plurality of means for retaining an electrical signal being arranged in an order along a path, wherein each of said plurality of means for retaining an electrical signal can be independently set in either of said first or said second states; a serial input to said plurality of means for retaining an electrical signal; means for sequentially setting each of said plurality of means for retaining an electrical signal in either said first or said second state in response to state signals input at said serial input, wherein said state of each of said means for retaining an electrical signal are set in reverse of said order and said state signal for a particular of said means for retaining an electrical signal must first pass through all of said plurality of means for retaining an electrical signal which are on said path and between said serial input and said particular of said means for retaining an electrical signal; and an additional means for retaining an electrical signal indicative of either a first or a second state, wherein said state of said additional means for retaining an electrical signal can be set as part of said sequence of setting said state in each of said plurality of means for retaining an electrical signal, and wherein said state of said additional means for retaining an electrical signal is also indicative of two different operational modes of said register. - View Dependent Claims (14, 15)
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Specification