Serial bus interface system for data communication using two-wire line as clock bus and data bus

• US 4,847,867 A
• Filed: 09/01/1987
• Issued: 07/11/1989
• Est. Priority Date: 09/01/1986
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nasu, Masaki, Maehashi, Yukio, Yoshizawa, Kazutoshi, Katori, Shigetatsu
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/091,803
• Time in Patent Office: 679 Days
• Field of Search: 375/29-36, 375/106-107, 370/24-29, 370/85, 340/825.2, 340/825.21
• US Class Current: 375/257
• CPC Class Codes: G06F 13/4077 Precharging or discharging
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

Claims

1. A communication system comprising:

a plurality of stations,

a single clock wire interconnecting said stations, and

a single data wire interconnecting said stations, wherein

at least one of said stations operates as a master station, a pair of stations in said stations operate as a transmitting station and a receiving station, respectively,

said master station including a push-pull transistor circuit for driving said single clock wire to output a clock signal on said single clock wire,

said single data wire being coupled to wired logic means, said transmitting station including a first shift register temporarily storing data to be transmitted, means coupled to said single clock wire for supplying said clock signal to said first shift register, said first shift register shifting and outputting each bit of said data in synchronism with one of falling and leading edges of the associated clock pulse of said clock signal and means coupled between said first shift register and said single data line for transmitting each bit of said data outputted from said first shift register on said single data wire,

said receiving station including a second shift register, means coupled to said single clock wire for supplying said clock signal on said single clock wire to said second shift register, and means coupled between said single data wire and said second shift register for supplying said second shift register with each bit of said data on said single data wire, said second shift register receiving each bit of said data supplied thereto in synchronism with the other of said falling and leading edges of the associated clock pulse of said clock signal.

2. The system as claimed in claim 1, wherein said push-pull transistor circuit has a first transistor connected between a first power terminal and said single clock wire and a second transistor connected between a second power terminal and said single clock wire, and said master station further includes means for turning ON one of said first and second transistors.

3. The system as claimed in claim 2, wherein said first transistor is of one conductivity type and said second transistor is of an opposite conductivity type.

4. The system as claimed in claim 2, wherein logic means comprises a resistor connected between said single data wire and said first power terminal and each of said stations includes a third transistor connected between said single data wire and said second power terminal.

5. A communication system comprising:

a plurality of stations, each of said stations including first and second terminals;

a first wire interconnecting said first terminals of said stations;

a second wire interconnecting said second terminals of said stations; and

an impedance element connected between said second wire and a power terminal;

wherein

one of said stations operates as a master station and each of the remaining stations operate as a slave station;

said master station further including a transistor push-pull circuit connected to said first terminal thereof and driving said first wire to output a clock signal on said first wire or to maintain said first wire at a first logic level, means for outputting a first signal on said second wire to change said second wire from said first logic level to a second logic level while said first wire is maintained at said first logic level, means for outputting a second signal on said second wire to change said second wire from said second logic level to said first logic level while said first wire is maintained at said first logic level, means for transmitting an address signal on said second wire in synchronism with said clock signal after both of said first and second signals are outputted on said second wire, said address signal containing first information for selecting one of said slave stations, means for transmitting a command signal on said second wire in synchronism with said clock signal after said first signal is outputted on said second wire without said second signal being outputted, said command signal containing second information for designating the slave station to be selected to a data receiving mode or a data transmitting mode, and means for transmitting a master data signal on said second wire in synchronism with said clock signal when the slave station to be selected is designated to said data receiving mode;

each of said slave stations further including means coupled to said first and second terminals thereof for detecting whether said first signal is outputted on said second wire to produce a first detection signal, means coupled to said first and second terminals thereof for detecting whether said second signal is outputted on said second wire to produce a second detection signal, and means coupled to said first and second terminals for receiving said address signal on said second wire in synchronism with said clock signal on said first wire when both of said first and second detection signals are produced, and wherein

each of said slave stations means for comparing said first information contained in the received address signal with an individually allotted address information to produce a third detection signal when said first information is coincident with the individually allotted address information, means coupled to said first and second terminals thereof for receiving said command signal on said second wire in synchronism with said clock signal on said first wire when both of said first and third detection signals are produced, means for detecting which of said data receiving mode and said data transmitting mode is designated in response to said second information contained in the received command signal, means coupled to said first and second terminals thereof for receiving said master data signal on said second wire in synchronism with said clock signal on said first wire when said data receiving mode is designated, and means coupled to said first and second terminals thereof for transmitting a slave data signal on said second wire in synchronism with said clock signal on said first wire when said data transmitting mode is designated; and

wherein

said master station further includes means coupled to said second terminal thereof for receiving said slave data signal on said second wire in synchronism with said clock signal.

6. The system as claimed in claim 5, wherein said transistor push-pull circuit has a first transistor connected between said first terminal and said power terminal and a second transistor connected between said first terminal and a reference terminal and each of said stations further includes a third transistor connected between said second terminal and said reference terminal.

7. The system as claimed in claim 6, wherein said first transistor is of one conductivity type and said second and third transistors are of an opposite conductivity type.

8. A data processor for communicating with at least one external device through a clock wire and a data wire, said data processor comprising;

a first terminal to be connected to said external device through said clock wire,

a second terminal to be connected to said external device through said data wire,

a third terminal applied with a power voltage,

a fourth terminal applied with a reference voltage,

a first transistor connected between said first and third terminals,

a second transistor connected between said first and fourth terminals,

a third transistor connected between said second and fourth terminals,

a mode register,

means for setting said mode register in a master operation mode and for resetting said mode register in a slave operation mode,

a flag register,

means for setting said flag register in a data transmitting operation mode and for resetting said flag register in a data receiving operation mode,

a shift register having a shift clock mode supplied with a shift clock signal,

a data input node,

a data output node, and

a set of data input/output nodes,

said shift register outputting, in said data transmitting operation mode, data stored therein to said data output mode one bit at a time in synchronism with said shift clock signal and introducing, in said data receiving operation mode, data supplied to said data input node one bit at a time in synchronism with said shift clock signal,

said processor further comprising;

means coupled to said data output node of said shift register for turning said third transistor ON or OFF in response to data outputted from said shift register when said flag register is set to thereby transmit data outputted from said shift register on said data wire via said second terminal and for turning said third transistor OFF when said flag register is reset,

means coupled between said second terminal and said data input mode of said shift register for supplying in said data receiving operation mode, said data input mode with data transferred to said second terminal from said external device via said data wire,

means for writing data to be transmitted into said shift register via said set of data input/output modes in said data transmitting operation mode,

means for reading data out of said shift register via said set of data input/output modes in said data transmitting operation mode,

means for producing a serial clock signal,

means for alternately turning said first and second transistors ON in response to said serial clock signal when said mode register is set to thereby output said serial clock signal on said clock wire via said first terminal and for turning both of said first and second transistors OFF when said mode register is reset,

means for supplying, in said master operation mode, said serial clock signal to said shift clock mode of said shift register as said shift clock signal, and

means coupled to said first terminal for supplying, in said slave operation mode, said shift clock mode of said shift register with a clock signal transferred to said first terminal front said external device via said clock wire.

9. A communication system comprising a master station including:

first and second terminals;

a plurality of slave stations, each of which includes third and fourth terminals;

a clock wire interconnecting said first terminal of said master station and said third terminals of said slave stations;

a data wire interconnecting said second terminal of said master station and said fourth terminals of said slave stations; and

a resistor connecting said data wire to a power terminal;

said master station further including;

a transistor push-pull circuit connected to said first terminal and driving said clock wire to output a serial clock signal on said clock wire or to maintain said clock wire at one of a plurality of binary logic levels,

means coupled to said second terminal for outputting a first signal to change said data wire from said one logic level to the other logic level while said clock wire is maintained at said one logic level,

means for outputting a second signal to change said data wire from said other logic level to said one logic level while said clock wire is maintained at said one logic level,

means coupled to said second terminal for transmitting an address signal on said data wire in synchronism with said serial clock signal after both of said first and second signals are outputted, said address signal contained information for selecting one of said slave stations,

means coupled to said second terminal for transmitting a command signal on said data wire in synchronism with said serial clock signal after only one of said first and second signals are outputted,

said command signal containing information for designating the slave station to b selected to a data receiving mode or a data transmitting mode, and

means coupled to said second terminal for transmitting a data signal on said data wire in synchronism with said serial clock signal without both of said first and second signals being outputted, said data signal containing information to be processed by the slave station to be selected; and

wherein

each of said slave stations further includes first and second flags, means coupled to said third and fourth terminals for detecting that said first signal is outputted and for setting said first flag when said first signal is detected to be outputted, means coupled to said third and fourth terminals for detecting that said second signal is outputted and for setting said second flag when said second signal is detected to be outputted, means coupled to said third and fourth terminals for receiving the signal on said data wire in synchronism with said serial clock signal on said clock wire, and means coupled to said first and second flags and to said receiving means for detecting that said receiving means has received which of said address, command and data signals in response to contents of said first and second flags.

10. The system as claimed in claim 9, wherein each of said slave stations further includes means for transmitting an acknowledgement signal on said data wire in synchronism with said serial clock signal on said clock wire after any one of said address, command and data signal being received in said receiving means and means for resetting both or one of said fist and second flags after said address or command signal is received in said receiving means.