Differential phase modulation demodulator

• US 4,849,706 A
• Filed: 07/01/1988
• Issued: 07/18/1989
• Est. Priority Date: 07/01/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mandalia, Baiju D., Davis, Gordon T.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/214,250
• Time in Patent Office: 382 Days
• Field of Search: 329/104, 329/105, 329/110, 329/112, 329/126, 329/137, 329/145, 375/80, 375/82, 375/83-87, 375/94, 455/214
• US Class Current: 329/304
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

A demodulator mechanism is described for demodulating differential phase modulated carrier signals. This demodulator mechanism solves the following two equations:

U=K[R2(R1-S1)+S2(R1+S1)]

V=K[R2(R1+S1)-S2(R1-S1)]

where U denotes a first baseband modulation component of the received carrier signal, V denotes a second baseband modulation component of the received carrier signal, K denotes a proportionality constant, R2 denotes the received carrier signal, R1 denotes a delayed version of the received carrier signal which has been delayed by one baud period relative to the received carrier signal, S2 denotes a 90° phase shifted version of the received carrier signal and S1 denotes a delayed version of the phase shifted carrier signal which has been delayed by one baud period relative to the phase shifted carrier signal. Both analog and digital implementations of the demodulator mechanism are described. Double frequency terms are automatically cancelled and no post detection filtering is required for this purpose.

Claims

1. A demodulator mechanism for demodulating a phase modulated carrier signal comprising:

input means for supplying an input carrier signal which is phase modulated;

phase shift means responsive to the input carrier signal for producing a phase shifted carrier signal;

first delay means responsive to the input carrier signal for producing a delayed input carrier signal;

second delay means responsive to the phase shifted carrier signal for producing a delayed phase shifted carrier signal;

signal combining means jointly responsive to both the delayed input carrier signal and the delayed phase shifted carrier signal for producing a carrier reference signal;

and signal modulator means jointly responsive to both the input carrier signal and the carrier reference signal for producing a demodulated signal representing a baseband modulation component of the input carrier signal.

2. A demodulator mechanism in accordance with claim 1 wherein the signals produced by the first and second delay means are delayed by one baud period relative to their respective input signals.

3. A demodulator mechanism for demodulating a phase modulated carrier signal comprising:

input means for supplying an input carrier signal which is phase modulated;

phase shift means responsive to the input carrier signal for producing a phase shifted carrier signal;

first delay means responsive to the input carrier signal for producing a delayed input carrier signal;

second delay means responsive to the phase shifted carrier signal for producing a delayed phase shifted carrier signal;

signal subtracting means responsive to the delayed input carrier signal and the delayed phase shifted carrier signal for producing a first carrier reference signal;

signal adding means responsive to the delayed input carrier signal and the delayed phase shifted carrier signal for producing a second carrier reference signal;

and signal modulator means responsive to the input carrier signal, the first carrier reference signal, the phase shifted carrier signal and the second carrier reference signal for producing a demodulated baseband signal representing a baseband modulation component of the input carrier signal.

4. A demodulator mechanism in accordance with claim 3 wherein the signal modulator means includes:

a first modulator responsive to the input carrier signal and one of the first and second carrier reference signals for producing a first product signal;

a second modulator responsive to the phase shifted carrier signal and the other of the first and second carrier reference signals for producing a second product signal;

and signal combining means responsive to the first and second product signals for producing the demodulated baseband signal.

5. A demodulator mechanism in accordance with claim 4 wherein;

the first modulator is responsive to the input carrier signal and the first carrier reference signal;

the second modulator is responsive to the phase shifted carrier signal and the second carrier reference signal;

and the signal combining means is a signal adding means for adding the first and second product signals to produce the demodulated baseband signal.

6. A demodulator mechanism in accordance with claim 4 herein:

the first modulator is responsive to the input carrier signal and the second carrier reference signal;

the second modulator is responsive to the phase shifted carrier signal and the first carrier reference signal;

and the signal combining means is a signal subtracting means for subtracting the first and second product signals to produce the demodulated baseband signal.

7. A demodulator mechanism in accordance with claim 3 and further including second signal modulator means responsive to the input carrier signal, the second carrier reference signal, the phase shifted carrier signal and the first carrier reference signal for producing a second demodulated baseband signal representing a second baseband modulation component of the input carrier signal.

8. A demodulator mechanism for demodulating a phase modulated carrier signal comprising:

input means for supplying an input carrier signal which is phase modulated;

phase shift means responsive to the input carrier signal for producing a phase shifted carrier signal;

first delay means responsive to the input carrier signal for producing a delayed input carrier signal;

second delay means responsive to the phase shifted carrier signal for producing a delayed phase shifted carrier signal;

signal subtracting means responsive to the delayed input carrier signal and the delayed phase shifted carrier signal for producing a first carrier reference signal;

signal adding means responsive to the delayed input carrier signal and the delayed phase shifted carrier signal for producing a second carrier reference signal;

a first modulator responsive to the input carrier signal and the first carrier reference signal for producing a first product signal;

a second modulator responsive to the phase shifted carrier signal and the second carrier reference signal for producing a second product signal;

signal adding means responsive to the first and second product signals for producing a first demodulated signal representing a first baseband modulation component of the input carrier signal;

a third modulator responsive to the input carrier signal and the second carrier reference signal for producing a third product signal;

a fourth modulator responsive to the phase shifted input carrier signal and the first carrier reference signal for producing a fourth product signal;

and signal subtracting means responsive to the third and fourth product signals for producing a second demodulated signal representing a second baseband modulation component of the input carrier signal.

9. A demodulator mechanism for demodulating a phase modulated carrier signal comprising:

input means for supplying an input carrier signal which is phase modulated;

sampling means for periodically sampling the input carrier signal and producing for each sample a multi-bit input carrier number representing the amplitude value of the input carrier signal at the moment of sampling;

storage means for storing the input carrier numbers produced by the sampling means;

processor means for performing arithmetic operations on multi-bit numbers;

first control means for causing the processor means to produce from the stored input carrier numbers multi-bit phase shifted carrier numbers representing amplitude values of a phase shifted version of the input carrier signal;

and second control means for causing the processor means to combine the input carrier numbers and the phase shifted carrier numbers for a first time interval with the input carrier numbers for a second time interval for producing multi-bit demodulated signal numbers representing amplitude values of a baseband modulation component of the input carrier signal.

10. A demodulator mechanism for demodulating a phase modulated carrier signal comprising:

input means for supplying an input carrier signal which is phase modulated;

sampling means for periodically sampling the input carrier signal and producing for each sample a multi-bit input carrier number representing the amplitude value of the input carrier signal at the moment of sampling;

storage means for storing the input carrier numbers produced by the sampling means;

processor means for performing arithmetic operations on multi-bit numbers;

first control means for causing the processor means to produce from the stored input carrier numbers multi-bit phase shifted carrier numbers representing amplitude values of a phase shifted version of the input carrier signal;

and second control means for causing the processor means to combine at least one of the input carrier numbers and at least one of the phase shifted carrier numbers for a first time interval with at least one of the input carrier numbers for a second time interval for producing at least one multi-bit demodulated signal number representing an amplitude value of a baseband modulation component of the input carrier signal.

11. A demodulator mechanism for demodulating a phase modulated carrier signal comprising:

input means for supplying an input carrier signal which is phase modulated;

sampling means for periodically sampling the input carrier signal and producing for each sample a multi-bit input carrier number representing the amplitude value of the input carrier signal at the moment of sampling;

storage means for storing the input carrier numbers produced by the sampling means;

processor means for performing arithmetic operations on multi-bit numbers;

first control means for causing the processor means to produce from the stored input carrier numbers multi-bit phase shifted carrier numbers representing amplitude values of a phase shifted version of the input carrier signal;

and second control means for causing the processor means to combine the input carrier numbers and the phase shifted carrier numbers for a first baud period with the input carrier numbers and the phase shifted carrier numbers for a second baud period for producing multi-bit demodulated baseband signal numbers representing amplitude values of a baseband modulation component of the input carrier signal.

12. A demodulator mechanism in accordance with claim 11 wherein the second control means causes the processor means to combine the various numbers in accordance with the following relationship:

space="preserve" listing-type="equation">U=K[R2(R1-S1)+S2(R1+S1)]

where U denotes a demodulated baseband signal number, K denotes a proportionality constant, R1 and S1 respectively denote the input carrier number and the phase shifted carrier number for a given sampling interval for a first baud period, and R2 and S2 respectively denote the input carrier number and the phase shifted carrier number for the corresponding sampling interval in the next baud period.

13. A demodulator mechanism in accordance with claim 11 wherein the second control means causes the processor means to combine the various numbers in accordance with the following relationship:

space="preserve" listing-type="equation">V=K[R2(R1+S1)-S2(R1-S1)]

where V denotes a demodulated baseband signal number, K denotes a proportionality constant, R1 and S1 respectively denote the input carrier number and the phase shifted carrier number for a given sampling interval for a first baud period, and R2 and S2 respectively denote the input carrier number and the phase shifted carrier number for the corresponding sampling interval in the next baud period.

14. A demodulator mechanism for demodulating a phase modulated carrier signal comprising:

input means for supplying an input carrier signal which is phase modulated;

sampling means for periodically sampling the input carrier signal and producing for each sample a multi-bit input carrier number representing the amplitude value of the input carrier signal at the moment of sampling;

storage means for storing the input carrier numbers produced by the sampling means;

processor means for performing arithmetic operations on multi-bit numbers,

first control means for causing the processor means to produce from the stored input carrier numbers multi-bit phase shifted carrier numbers representing amplitude values of a phase shifted version of the input carrier signal;

second control means for causing the processor means to combine the input carrier numbers and the phase shifted carrier numbers for a first baud period with the input carrier numbers and the phase shifted carrier numbers for a second baud period for producing first multi-bit demodulated signal numbers representing amplitude values of a first baseband modulation component of the input carrier signal;

and third control means for causing the processor means to combine the input carrier numbers and the phase shifted carrier numbers for a first baud period with the input carrier numbers and the phase shifted carrier numbers for a second baud period for producing second multi-bit demodulated signal numbers representing amplitude values of a second baseband modulation component of the input carrier signal.

15. A demodulator mechanism in accordance with claim 14 wherein:

the second control means causes the processor means to combine the various numbers in accordance with the following relationship;

space="preserve" listing-type="equation">U=K[R2(R1-S1)+S2(R1+S1)]

and the third control means causes the processor means to combine the various numbers in accordance with the following relationship;

space="preserve" listing-type="equation">V=K[R2(R1+S1)-S2(R1-S1)]

where U denotes a demodulated signal number for a first baseband modulation component of the input carrier signal, V denotes a demodulated signal number for a second baseband modulation component of the input carrier signal, K denotes a proportionality constant, R1 and S1 respectively denote the iput carrier number and the phase shifted carrier number for a given sampling interval for a first baud period, and R2 and S2 respectively denote the input carrier number and the phase shifted carrier number for the corresponding sampling interval in the next baud period.