Digital engine analyzer

• US 4,849,744 A
• Filed: 10/09/1987
• Issued: 07/18/1989
• Est. Priority Date: 08/23/1985
• Status: Expired due to Term

• Current Assignee: Snap-On Incorporated
• Original Assignee: Snap-On Tools Company LLC (Snap-On Incorporated)
• Inventors: Govekar, Craig F., Putrow, Michael C.
• Primary Examiner(s): Brigance, Gerald L.
• Application Number:
  US07/088,888
• Time in Patent Office: 648 Days
• Field of Search: 340/721, 340/731, 340/735, 340/748, 340/750, 340/722, 324/378, 324/379
• US Class Current: 345/10
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: F02P 17/00 Testing of ignition installations, e.g. in combination with adjusting testing fuel injection apparatus F02M65/00; testing ignition installations in general F23Q23/00; Testing of ignition timing in compression-ignition engines
• CPC Class Codes: G01R 13/345 for displaying sampled signals by using digital processors by intermediate A.D. and D.A. convertors (control circuits for CRT indicators)
• CPC Class Codes: G09G 1/162 for displaying digital inputs as analog magnitudes, e.g. curves, bar graphs, coordinate axes, singly or in combination with alpha-numeric characters cathode-ray oscilloscopes for displaying analog inputs, singly or in combination with alpha-numeric characters G01R13/20; television receiver circuitry for displaying supplementary, e.g. alpha-numeric, information H04N5/445

Abstract

A microprocessor controlled digital engine analyzer receives analog input signals from an engine being analyzed, engine parameter data entered via a keyboard, and function data, selecting one of several operating modes for the analyzer and which information is to be displayed, entered via the keyboard, and displays on a CRT screen the selected information such as cylinder firing order,RPM, Dwell, KV and DC volts, alphanumerically, information such as primary and secondary ignition and voltage, alternator and fuel injector information through the use of continuous waveform patterns, and additional information pertaining to Dwell, KV and Cylinder Shorting through the use of bar graphs. The waveform pattern data derived form the analog input signals is stored in a dual bank waveform memory and read out for display on the CRT screen under hardware control, and address data representing alphanumeric data and screen formats for the various operating modes to be displayed is stored in a dual bank display memory for application to a character generator, a bank switching arrangement being used for both the waveform memory and the display memory to enable the banks of each memory to be alternately written to and read from. A main microprocessor receives and processes analog input signals, other than the waveform pattern signals, and a display microprocessor receives numerical data from the main microprocessor and causes display of the numerical data on the CRT screen.

Claims

1. An engine analyzer for analyzing analog signals produced by an internal combustion engine, comprising an analog-to-digital converter for converting the analog signals into digital signals, a cathode ray tube including a screen and an electron beam which is swept across said screen, said screen being defined by a plurality of beam rows and a plurality of beam columns, said screen being further divided into a plurality of character rows and a plurality of character columns defining a plurality of character areas, the electron beam scanning said screen along a row in one row after the next, the electron beam being selectively operable to illuminate selected points at the intersections of the beam rows and the beam columns, monitor means for monitoring the beam row in which the electron beam is sweeping at an instant of time, character ROM means having stored at a multiplicity of locations therein character matrices respectively corresponding to a multiplicity of characters and respectively being accessed by a multiplicity of character access signals, each character matrix being defined by m rows and n columns, memory means coupled to said character ROM means for storing character access signals for the character matrices to be displayed in the character areas, characters address means for addressing said memory means with respect to each character matrix one after another in each character now one character row after the other for supplying character matrices corresponding to the characters to be displayed respectively in the character areas, matrix row address means coupled to said character ROM means for causing one row of data for each character matrix selected by said memory means to be simultaneously released, said matrix row address means addressing the data in the first and last rows of each character matrix selected of said character ROM means for a single beam row and said matrix row address means addressing the same data in said character ROM means for two consecutive beam rows for the intermediate ones of said rows of each character matrix selected, whereby each character displayed is increased in vertical height for only said intermediate beam rows and the number of character rows displayed on the screen is 2(m-1), and data generator means coupled to said character ROM means for changing the data simultaneously released therefrom into a sequence of data.

2. The engine analyzer of claim 1, wherein said character address means includes a column address portion that increments at a rate no greater than the scanning rate of the electron beam divided by the number of beam columns in each character area, and a row address portion that increments at a rate equal to the output of said monitor means divided by the number of beam rows in each character area.

3. The engine analyzer of claim 1, and further comprising screen ROM means having stored at a multiplicity of locations therein data respectively corresponding to a multiplicity of formats to appear on said screen and respectively being accessed by a multiplicity of screen access signals, a microprocessor for developing alphanumeric information from the analog signals, the formats and the alphanumeric information being written into said memory means under control of said microprocessor.

4. The engine analyzer of claim 1, wherein said matrix row address means includes a counter which is advanced by the leading edge of a clock pulse to a count of m and is then reset by a reset pulse, the initial count up from the reset state of the counter being advanced one half clock cycle and the counter being reset one half clock cycle after it registers a count of m whereby said matrix row address means addresses the same data in said character ROM means for two consecutive beam rows except for the first and last rows.

5. The engine analyzer of claim 1, wherein said data generator means is clocked at one-half the scanning rate of the electron beam so that each pair of adjacent intersections is illuminated or not, thereby doubling the width of each character.

6. The engine analyzer of claim 1, wherein the number, m, of rows of each character matrix is 9 and the number of character rows displayed on the screen is 16, and the number, n, of columns of each character matrix is 7, said data generator means being clocked at one-half the scanning rate of the electron beam.