Multiple memory image display apparatus

• US 4,849,745 A
• Filed: 01/14/1988
• Issued: 07/18/1989
• Est. Priority Date: 06/15/1984
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Satou, Hitoshi
• Primary Examiner(s): Caldwell, Sr., John W.
• Assistant Examiner(s): Brier, Jeffery A.
• Application Number:
  US07/144,728
• Time in Patent Office: 551 Days
• Field of Search: 340/721, 340/723, 340/724, 340/725, 340/744, 340/798, 340/799, 364/413, 364/414, 364/415, 364/518, 364/521
• US Class Current: 345/563
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

In an image display apparatus, a frame memory for storing original data and a display memory for storing display data are used as memories for storing image data. The image data is read out from the display memory and is displayed by a display system. When image data transfer from the frame memory to the display memory is performed through a programmable data conversion memory, data conversion is performed as image processing. The image display apparatus has a masking memory having an image area corresponding to the frame memory. The masking memory stores image data indicating a desired transfer area in the frame memory as a mask pattern in advance. The image data transfer from the frame memory to the display memory is performed only for an area designated by the masking memory.

Claims

1. A multiple memory image display apparatus comprising:

a frame memory for storing first image data;

data converting means for converting the first image data to second image data in a predetermined format for display as a visual image corresponding to the first image data and for generating the second image data in response to the first image data being read out from said frame memory and transferred to said data converting means;

a display memory, having a smaller memory capacity than said frame memory, for temporarily storing the second image data transferred from said data converting means;

displaying means for reading out the second image data from said display memory in synchronism with a predetermined synchronizing signal and for displaying the visual image corresponding to the converted first image data;

a masking memory, having a matrix structure corresponding to said frame memory, for storing masking pattern data corresponding to an image transfer area representing a part of the first image data which is to be transferred and displayed as a visual image;

address signal generating means, responsive to the readout operation of the second image data from said display memory, for generating a read address signal in synchronism with the synchronizing signal, said read address signal being altered responsive to every occurrence of said synchronizing signal, said read address signal being sent to both said frame memory and said masking memory, said read address signal for transferrring the part of the first image data stored in said frame memory set by said image transfer area; and

control means for controlling and synchronizing the reading of the first image data from said frame memory into said display memory and the reading of the masking pattern data from said masking memory into said display memory with the writing of a portion of a second image data corresponding to the masking pattern data from said data converting means into said display memory wherein said second image data are switched at a high speed in a cine type display.

2. An apparatus according to claim 1, wherein said data converting means includes a data conversion table which is programmable.

3. An apparatus according to claim 1, wherein said data converting means includes a memory for storing the second image data at an address corresponding to the value of the first image data.

4. An apparatus according to claim 1, wherein the masking pattern data stored in said masking memory can be arbitrarily programmed by an external circuit.

5. An apparatus according to claim 1, wherein said address signal generating means can change a relative position of said image transfer area in said masking memory by an external circuit.

6. An apparatus according to claim 1, wherein said displaying means displays an image in response to a non-interlaced scanning method of scanning.

7. An apparatus according to claim 1, wherein said displaying means displays an image in response to an interlaced scanning method of scanning.

8. An apparatus according to claim 1, wherein said displaying means displays an image in response to an interlaced scanning method of scanning, and said display memory comprising an even-field memory portion and an odd-field memory portion.

9. An apparatus according to claim 1, wherein said displaying means displays an image in response to an interlaced scanning method of scanning said display memory comprises an even-field memory portion and an odd-field memory portion, and said address signal generating means generates an even-field address during an even-field display period and an odd-field address during an odd-field display.