Computer address modification system with optional DMA paging

• US 4,849,875 A
• Filed: 08/10/1987
• Issued: 07/18/1989
• Est. Priority Date: 03/03/1987
• Status: Expired due to Fees

• Current Assignee: Tandon Corporation (TSL Holdings, Inc.)
• Original Assignee: Tandon Corporation (TSL Holdings, Inc.)
• Inventors: Swinton, William G., Fairman, Bruce A., Taylor, Robert G. Jr., Larsen, Allen J.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Mohamed, Ayni
• Application Number:
  US07/084,318
• Time in Patent Office: 708 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/235
• US Class Current: 710/26
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 2212/206 Memory mapped I/O

Abstract

A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses in 16K blocks which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

Claims

1. A computer address modification system for modification of a portion of a computer address received from a computer system comprising:

a mapper store having a plurality of addressable storage locations, each of which corresponds to a block of addresses, stores address information representing at least a portion of a translated address for the corresponding block of addresses, and outputs the stored address information in response to a portion of an address received from the computer system that identifies the corresponding block addresses;

a page store having a plurality of addressable storage locations, each of which corresponds to a direct memory access channel of the computer system, stores address information representing at least a portion of an address for assertion during a direct memory access using the corresponding direct memory access channel, and outputs the stored address information in response to an occurrence of a direct memory access on the corresponding channel;

a control circuit receiving a portion of the received computer address sufficient to identify a block of addresses within a plurality of blocks of addresses, receiving from the computer system signals indicating an occurrence of a direct memory access and the channel on which a direct memory access occurs, receiving from the computer system a page store enable signal that is selectively in an active or inactive state and independent of any address location indicated by the received computer address, and receiving stored address information output from the page store;

the control circuit being operative to output system address data representing at least a portion of a computer address as a substitute for the received address portion, the system address data being, when a direct memory access channel is active and the page store enable signal has an active state, the output from the page store storage location corresponding to the active channel, and when the direct memory access channel is inactive the output from a mapper store location corresponding to a block of addresses indicated by the received computer address portion.

2. A computer address modification system according to claim 1, further comprising a control register providing storage for at least one control state defined by information received from the computer system, one of the control states being a translation enable state, the control circuit including a circuit blocking substitution of a translated address portion stored in the mapper store for the received address portion unless the stored translation enable state indicates that translation is enabled.

3. A computer address modification system according to claim 1 further comprising a DMA mode register having storage for a plurality of enable signals received from the computer system, each corresponding to a different direct memory access channel, the control circuit including a circuit responsive to the DMA mode register to disable substitution of an address portion stored in the page store for a DMA address portion unless the stored enable signal corresponding to an active channel indicates that the substitution is enabled.

4. A computer address modification system receiving and selectively modifying a portion of an address from a computer system comprising:

a page store having a plurality of addressable storage locations corresponding to each of a plurality of different direct memory access channels with one of the storage locations corresponding to each channel being a first storage location;

a DMA mode register storing for each channel a channel enable signal received from the computer system;

and a control circuit responsive to a page register enable signal received from the counter system, to the received portion of an address and to the DMA mode register to control selective modification of the portions of received addresses, the control circuit commanding operation in an extended mode when the page register enable signal is active and a direct memory access channel is active while the corresponding channel enable signal for the active channel stored by the DMA mode register has an active state by providing as a portion of the computer address signals, data stored in one of the addressable page store storage locations which corresponds to the active channel with the one addressable storage location being selected in response to at least a portion of the received computer address signals; and

the control circuit inhibiting the providing of data stored in the page store as a portion of the computer address signals when the page register enable signal is inactive, when the channel enable signal corresponding to the current DMA channel has an inactive state and when no direct memory access channel is active.

5. A computer address modification system according to claim 4, wherein the provided data is substituted for at least the portion of the computer address signal which the control circuit responds to in selecting the one addressable storage location.

6. A computer address modification system according to claim 4 wherein the control circuit is responsive to an active state of the page register enable signal and an inactive state of a stored channel enable signal for an active channel by commanding operation in a special clone mode by providing as a portion of the computer address signals, data stored in the first of the plurality of addressable page storage locations which corresponds to the active channel.

7. A computer address modification system according to claim 4 further comprising:

a mapping store storing a plurality of computer address portions for substitution in place of at least a portion of a computer address;

a control store storing a mapping store enable signal; and

the control circuit responding to an inactive state of the page register enable signal and an active state of the mapping store enable signal by commanding operation in a mapped clone mode by providing as a portion of the computer address signals one of the computer address portions stored in the mapping store with the one portion being selected in response to a portion of the received computer address signals.

8. A computer address modification system according to claim 7 wherein the control circuit responds to an inactive state of the page register enable signal by disabling substitution of data stored in the page store for the received portion of a computer address without disabling substitution of data stored in the mapping store for the received portion of a computer address.

9. A computer address modification system according to claim 7 wherein the control circuit responds to an inactive state of the stored mapping store enable signal by disabling any substitution of data stored in the mapping store for any portion of a computer address.

10. A computer address modification system receiving and selectively modifying address data from a computer system, the address modification system comprising:

a page store having a plurality of addressable storage locations storing computer address data, each storage location corresponding to one of a plurality of different direct memory access channels with one of the storage locations corresponding to each channel being a first storage location;

a DMA mode register storing and providing as an output a channel enable signal selectively enabling paging for each DMA channel;

a mapping store storing a plurality of storage locations, each storing computer address data for substitution in place of the received computer address data;

control store storing and providing as an output a mapping store enable signal; and

a control circuit responsive to the states of the channel enable signals, the mapping store enable signal and a page store enable signal received from a computer system to command operation in a selected one of a plurality of modes including (1) when the page store enable signal is active and a DMA channel activity signal indicates operation of a given DMA channel while the corresponding stored channel enable signal has an active state, an extended mode in which computer address data stored in the page store at one of the storage locations is provided as an output for use in forming at least a portion of a computer address, the storage location being selected from among the storage locations corresponding to the active channel in response to the received computer address data;

(2) when the page store enable signal is active and a DMA channel activity signal indicates operation of a given DMA channel while the corresponding stored channel enable signal has an inactive state, a special clone mode in which the computer address data stored in the page store at the first storage location corresponding to the active DMA channel is provided as an output for use in forming at least a portion of a computer address, (3) when the page store enable signal is inactive and the stored mapping store enable signal has an active state, a mapped clone mode in which computer address data stored in a mapping store storage location selected in response to the received computer address data is provided for use in forming at least a portion of a computer address, and (4) when the page store enable signal is inactive and the stored mapping store enable signal has an inactive state, a clone mode in which the received computer address data is output unchanged for use in forming at least a portion of a computer address.

11. A computer address modification system according to claim 10 wherein the control store stores a mapping redirection signal having a state which is either a redirection state or a nonredirection state, wherein the control circuit includes an interrupt processing detection circuit receiving signals indicating when an interrupt request is being responded to and generating an interrupt detected signal when a response to an interrupt request is indicated while the control store stores an interrupt redirection signal having a redirection state and wherein the control circuit operates when the interrupt detected signal is active while the stored interrupt redirection signal has a redirection state to inhibit providing address data stored in the mapping store as the output for use in forming at least a portion of a computer address.

12. A computer address modification system according to claim 11 wherein the control store has an address in a second address space that is distinguishable from the computer addresses and wherein the interrupt processing detection circuit responds to writing by the computer system of a selected state to a predetermined location within the control store using the address of the control store in the second address space by resetting the interrupt redirection signal to an inactive state.

13. A computer modification system for use with a computer system having first and second address spaces, the first address space having low, medium, high and extended address signal portions in respective order of significance, having DMA signals indicating DMA channel activity in the first address space and a circuit generating a page store enable signal selectively defining active and inactive states thereof, comprising:

a mapping store having a plurality of storage locations, each storage location storing a translation address having medium, high and extended address portions for a contiguous block of first address space addresses;

a writeable control store that is addressable in the second address space and includes at least one storage location including a mapping store unable location storing data defining a mapping store enable signal having selectable enable and disable states;

a page store having a plurality of storage locations, each storage location storing a paging address having medium, high and extended address portions for a contiguous block of first address space addresses, the page store having a plurality of storage locations corresponding to each DMA channel among a plurality of DMA channels with one of each plurality of storage locations being a first storage location;

a writeable DMA mode store that is addressable in the second address space and stores a channel enable signal defining a DMA paging channel enable state for each of a plurality of direct memory access channels; and

a control circuit controlling system operation in one of a plurality of modes including a clone mode and an extended mode,

(1) the control circuit operating in clone mode when the page store enable signal defines an inactive state and the stored mapping store enable signal has a disable state to provide as an output medium, high and extended address signal portions that are the same as received medium, high and extended address signal portions,

(2) the control circuit operating in mapped clone mode when the page store enable signal defines an inactive state and the mapping store enable signal has an enable state to provide as an output medium, high and extended address signal portions stored at a mapping store storage location determined in response to medium and high portions of a received address signal,

(3) the control circuit operating in special clone mode when the page store enable signal defines an active state, while the received DMA signals indicate that a DMA channel is active and the stored channel enable signal for the active channel has a state disabling paging to provide as an output medium, high and extended address signal portions stored at the first storage location among the plurality of storage locations corresponding to the active channel, and

(4) the control circuit operating in extended mode when the page store enable signal defines an active state while the received DMA signals indicate that a DMA channel is active and the stored channel enable signal for the active channel has a state enabling paging to provide as an output medium, high and extended address signal portions stored at a storage location among the plurality of storage locations corresponding to the active channel that is selected in response to the medium portion of a received address signal.

14. A computer address modification system according to claim 13 wherein the control circuit fails to provide as an output any address signal portion when the mapping store enable signal has an enable state and an extended portion of a received address signal has a state other than a predetermined state.

15. A computer address modification system according to claim 13 wherein the lower address portion of an address received from the computer system in the first address space defines a location within a 16K block of addresses where K equals 1024.

16. A computer address modification system according to claim 13 wherein the control store stores information defining an interrupt redirection signal and the control circuit includes means for detecting a response to an interrupt request and providing as an output medium, high and extended portions of addresses received from the computer system in the first address space after a response to an interrupt request is detected when the interrupt redirection signal has an active state.

17. A computer address modification system according to claim 13 wherein the control store stores a write enable signal selectively enabling writing of the mapping store and wherein the control store enables write accesses to the mapping store storage locations only when the write enable signal has a write enable state.

18. A computer address modification system according to claim 13 wherein the control store stores an extended address disable signal and the control circuit responds to an active state of the extended address disable signal by not providing any address portion as an output in response to an address signal received from the computer system having an extended portion having other than a given predetermined state.

19. A computer address modification system according to claim 18 wherein the given predetermined state of the extended portion of a received address is all zeros.

20. A computer address modification system according to claim 13 wherein the mapping store includes multiple sets of the plurality of storage locations with only one set being operative to provide translation address data at any given time, and wherein the control store stores data defining which set is active at any given time.