Connecting structure for connecting a memory unit to a memory unit controller

• US 4,849,944 A
• Filed: 08/14/1987
• Issued: 07/18/1989
• Est. Priority Date: 08/18/1986
• Status: Expired due to Term

• Current Assignee: Tokyo Electric Co.
• Original Assignee: Tokyo Electric Co., Ltd.
• Inventors: Matsushita, Tsuyoshi
• Primary Examiner(s): Fears, Terrell W.
• Assistant Examiner(s): Koval, Melissa J.
• Application Number:
  US07/085,187
• Time in Patent Office: 704 Days
• Field of Search: 365/189, 365/230, 365/228, 365/229, 365/1, 365/2, 365/51, 365/54, 365/226, 339/17 L, 339/17 LM, 439/59, 439/60, 439/61, 439/62
• US Class Current: 714/718
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/0746 Protection against transients, e.g. layout adapted for plugging of connector
• CPC Class Codes: H05K 2201/094 Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads using different types of conductors H05K2201/0391

Abstract

Grounding terminals of a memory unit are disposed at the opposite ends of an array of signal terminals of the memory unit, respectively, reception grounding terminals of a connector are disposed at the opposite ends of any array of reception signal terminals of the connector, respectively, the grounding terminals of the memory unit are connected to the reception grounding terminals of the connector, respectively, before the signal terminals of the memory unit are connected to the reception signal terminals of the connector in inserting the memory unit in the connector. Upon the insertion of the memory unit in the connector, the static electricity accumulate in the memory unit is discharged surely to a ground without affecting the semiconductor memory of the memory unit through the signal terminals and the reception signal terminals.

Claims

1. A connecting structure for electrically connecting a memory unit to an external control circuit, said connecting structure comprising:

a connector means having a plurality of in-line reception information signal terminals arranged in a straight line and connected to a control circuit, reception grounding terminals disposed at the opposite sides of said plurality of in-line reception information signal terminals, respectively, and connected to a ground; and

a memory terminal arrangement provided in a memory unit having an optionally reloadable semiconductor memory and adapted to be inserted in said connector, said memory terminal arrangement comprising;

a plurality of in-line output information signal terminals to be respectively connected to said reception information signal terminals, said in-line output signal terminals arranged along one side of said memory unit; and

, output grounding terminals disposed at the opposite ends of said plurality of said output information terminals, respectively, so as to be connected to said reception grounding terminals prior to said output information signal terminals being connected to said reception information signal terminals when said memory unit is inserted in said connector means.

2. A connecting structure according to claim 1 wherein the reception information signal terminals and reception grounding terminals of said connector are arranged in a straight line, and wherein the said output grounding terminals of said terminal arrangement project beyond and perpendicular to said plurality of in-line output information signal terminals in a direction away from said memory unit and towards said connector means when said memory unit is inserted in said connector means.

3. A connecting structure according to claim 1 wherein said output information signal terminals and output grounding terminals of said terminal arrangement of said memory unit are arranged in a straight line, and the reception grounding terminals of said connector project beyond and perpendicular to said reception information signal terminals so that said reception grounding terminals of said connector contact said output grounding terminals prior to said reception information signal terminals contacting said output information signal terminals upon insertion of said memory unit in said connector means.

4. A connecting structure for electrically connecting a memory unit to an external control circuit, said connecting structure comprising:

a connector having a plurality of in-line reception information signal terminals connected to a control circuit, reception check terminals connected to said control circuit and reception grounding terminals connected to a ground; and

a terminal arrangement provided in a memory unit having an optionally reloadable semiconductor memory, said terminal arrangement including output information signal terminals to be connected to said reception information signal terminals, respectively, arranged along one side of said memory units, output grounding terminals to be connected to said reception grounding terminals, respectively, arranged along said one side of said memory units, and, output check signal terminals arranged so as to be connected to said reception check signal terminals after said output information signal terminals have been connected to said reception information signal terminals, respectively and after said output grounding terminals have been connected to said connection grounding terminals.

5. A connecting structure according to claim 4 wherein said output check signal terminals are arranged in a pair at the opposite ends of said terminal arrangement provided in said memory unit, respectively.

6. A connecting structure according to claim 4 wherein said reception information signal terminals and said reception check signal terminals of said connector are arranged in a straight line and wherein said output information signal terminals and said grounding terminals project beyond and perpendicular to said output check signal terminals in a direction away from said memory unit and in a direction of insertion of said memory unit in said connector.

7. A connecting structure according to claim 6 wherein said output grounding terminals of said terminal arrangement of said memory unit are projected beyond and perpendicular to said output information signal terminals of said terminal arrangement in a direction away from said memory unit and in a direction of insertion of said memory unit in said connector.

8. A connecting structure according to claim 4 wherein said output information signals, said output check signal terminals and said output grounding terminals of said terminal arrangement of said memory unit are arranged in a straight line and wherein said reception information signal terminals and said reception grounding terminals of said connector project beyond and perpendicular to said reception check signal terminals of said connector in a direction of insertion of the memory unit in said connector.

9. A connecting structure according to claim 8 wherein said reception grounding terminals of said connector project beyond and perpendicular to said reception information signal terminals in a direction of insertion of the memory unit in said connector.

10. A memory system comprising:

a connector including a plurality of reception information signal terminals arranged in a straight line and connected to a control circuit, reception check signal terminals connected to said control circuit, and reception grounding terminals connected to a ground;

a switching device interposed between an electrically connected to said control circuit and to said reception information signal terminals;

a delay circuit interposed and electrically connected to said control circuit and to said reception check signal terminals, and adapted to provide a signal to close said switching circuit upon the reception of a connection signal through said reception check signal terminal; and

a memory unit including a reloadable semiconductor memory, a terminal arrangement disposed on one side of said reloadable semiconductor memory and including output information terminals to be connected to said reception information signal terminal, respectively, output grounding terminals to be connected to said reception grounding terminals, and output check signal terminals arranged so as to be connected to said reception check signal terminals after the output information signal terminals have been connected to said reception information signal terminals, respectively, and after said output check signal terminals have been connected to said reception check signal terminals, respectively.

11. A memory system according to claim 10 wherein said reception information signal terminals and said reception check signal terminals of said connector are arranged in a straight line with said output information signal terminals and said output grounding terminals projecting beyond and perpendicular to said output check signal terminals of said memory unit in a direction away from said memory unit and in the direction of insertion of said memory unit in said connector.

12. A memory system according to claim 11 wherein said output grounding terminals of said memory unit project beyond and perpendicular to said output information signal terminals of said memory unit in a direction of insertion of said memory unit in said connector.

13. The memory system according to claim 10 wherein said output information signal terminals, said output check terminals and said output grounding terminals of said memory unit are arranged in a straight line and wherein said reception information signal terminals and said reception grounding terminals of said connector project beyond and perpendicular to said reception check signal terminals of said connector in a direction which is both away from said memory unit and in the direction of insertion of said memory unit in said connector.

14. A memory system according to claim 13 wherein said reception grounding terminals of said connector project beyond and perpendicular to said reception information signal terminals of said connector in a direction of insertion of said memory unit in said connector.