Asynchronous digital time-division multiplexing system with distributed bus

• US 4,849,965 A
• Filed: 07/07/1987
• Issued: 07/18/1989
• Est. Priority Date: 10/14/1983
• Status: Expired due to Term

• Current Assignee: Denis Chomel, Herve Le Bris, Michel Devault, Yvon Rouaud
• Original Assignee: Denis Chomel, Herve Le Bris, Michel Devault, Yvon Rouaud
• Inventors: Rouaud, Yvon, Le Bris, Herve, Chomel, Denis, Devault, Michel
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US07/073,293
• Time in Patent Office: 742 Days
• US Class Current: 370/438
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: H04L 12/28 characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] wireless communication networks H04W ; arrangements for dividing the transmission path H04W40/00

Abstract

The system comprises a first unidirectional packet bus having a bit rate D, each packet including an e-bit identifier and a b-bit package, sources having differing bit rates d_i such that d_m ≦d_i ≦d_M <D, and access means for introducing packets from the sources into the first bus. An allocator located at the receiving end of the first bus builds up frames of identifiers identifying active sources. Each frame has a length T=b/d_m and is shared into N=d_M /d_m time slots. Each time slot has a period θ=b/d_M and includes a source identifier. The identifier for a same active source having a bit rate d_i is repeated in the frame n_i times such that n_i =d_i /d_m when d_i /d_m is an integer, or such that n_i =1+ integer part of (d_i /d_m) otherwise. The identifier frames are transmitted from the allocator into a second unidirectional bus distributed to all the access means. The access means of each source transmits a packet in the first bus whenever a b-bit package delivered from the source is received and an identifier of the source is detected in the second bus after package reception.

Claims

1. An asynchronous digital time-division multiplexing system, comprising

(a) plural data sources each having active and inactive states and being identified by respective identifiers, each active source supplying data bits with a corresponding bit rate, and said corresponding bit rates of said active sources being different therebetween;

(b) plural access means associated with said data sources, respectively, for linking each associated data source to an identifier bus and to a packet bus, each access means transmitting a packet into said packet bus in response to each identifier of said associated data source detected on said identifier bus, and each transmitted packet consisting of said identifier and a group of data bits delivered by said associated data source; and

(c) allocating means linked to said identifier bus for constituting identifier frames and transmitting said frames into said identifier bus; and

wherein

(d) each said identifier frame has a determined length and is composed of said identifiers corresponding to said active sources; and

(e) each identifier is repeated in said identifier frame a number of times approximately proportional to said bit rate of said active source corresponding to said identifier.

2. The system defined in claim 1, wherein said data sources have bit rates between a minimum bit rate d_m and a maximum bit rate N.d_m less than a predetermined bit rate D of said packet bus, where N is an integer, each identifier frame has a length equal to b/d_m and is split into N time slots, where b is a number of bits of said data bit group, each time slot has a period equal to b/(N.d_m) and includes one identifier, and further wherein each identifier has a bit rate d_i and is repeated in said frame n_i times such that n_i =d_i /d_m and n_i =l+(integer part of (d_i /d_m)) when d_i /d_m is equal to and different from an integer, respectively.

3. The system defined in claim 2, wherein said length of each frame time slot is equal to (e+b)/D increased by an amount equal to twice a bit propagation time in said identifier and packet buses between one of said access means nearest said allocating means and one of said access means farthest from said allocating means, where e is a number of bits of said identifier.

4. The system defined in claim 2, wherein said access means associated with said respective data source comprises means for detection said data source identifier in said identifier bus, means for assembling said data bits supplied progressively from said data source into said data bit groups, means for detecting each of said assembled data bit groups to deliver a triggering signal in response to each detected data source identifier following said data bit group assembly, and means for transmitting a packet made up of said data source identifier and said assembled data bit group into said packet bus in response to said triggering signal.

5. The system claimed in claim 4, wherein said assembling means in said access means comprises a first-in first-out (FIFO) buffer having a capacity equal at least to 2b bits.

6. An asynchronous digital time-division multiplexing system, comprising

(a) plural data sources each having active and inactive states and being identified by respective identifiers, each active source supplying data bits with a corresponding bit rate, and said corresponding bit rates of said active sources being different therebetween;

(b) plural access means associated with said data sources, respectively, for linking each associated data source to an identifier bus and to a packet bus, each access means transmitting a packet into said packet bus in response to each identifier of said associated data source detected on said identifier bus, and each transmitted packet consisting of said identifier and a group of data bits delivered by said associated data source; and

(c) allocating means, linked to said identifier bus for constituting identifier frames and transmitting said frames into said identifier bus, each identifier having a determined length and being composed of said identifiers corresponding to said active sources; and

wherein

(d) said data sources have bit rates between a minimum rate d_m and a maximum bit rate N.d_m less than a predetermined bit rate D of said packet bus, where N is an integer, each identifier frame has a length equal to b/d_m and is split into N time slots, where b is a number of bits of said data bit group, each time slot has a period equal to b/(N.d_m) and includes one identifier, and further wherein each identifier has a bit rate d_i and is repeated in said frame n_i times such that n_i =d_i /d_m and n_i =1+(integer part of (d_i /d_m)) when d_i /d_m is equal to and different from an integer, respectively; and

(e) said allocating means comprises means for storing identifiers in N memory-cells to constitute one frame, means for systematically providing N cell addresses to read said stored identifiers during first half-periods of said time slots in said frame, thereby to insert said read identifiers in said second bus during second half-periods of said frame time slots, respectively, and means for selectively providing an identifier writing address during one of the second half-periods of said frame time slots to write said identifier in said storing means during the second half-period of a following time slot.

7. The system defined in claim 6, wherein said length of each frame time slot is equal to (e+b)/D increased by an amount equal to twice a bit propagation time in said identifier and packet buses between one of said access means nearest said allocating means and one of said access means farthest from said allocating means, where e is a number of bits of said identifier.

8. The system defined in claim 6, wherein said access means associated with said respective data source comprises means for detecting said data source identifier in said identifier bus, means for assembling said data bits supplied progressively from said data source into said data bit groups, means for detecting each of said assembled data bit groups to deliver a triggering signal in response to each detected data source identifier following said data bit group assembly, and means for transmitting a packet made up of said data source identifier and said assembled data bit group into said packet bus in response to said triggering signal.

9. The system claimed in claim 8, wherein said assembling means in said access means comprises a first-in first-out (FIFO) buffer having a capacity equal at least to 2b bits.

10. The system claimed in 6, wherein said identifier bus further comprises a digital transmission line for transmiting pulses synchronous with said frame identifiers inserted during said second half-periods of said time slots and provided from said N-reading address providing means.