Single chip successive approximation analog-to-digital converter with trimmable and controllable digital-to-analog converter

• US 4,851,838 A
• Filed: 12/18/1987
• Issued: 07/25/1989
• Est. Priority Date: 12/18/1987
• Status: Expired due to Term

• Current Assignee: VTC, Inc. (Synaptics Incorporated)
• Original Assignee: VTC, Inc. (Synaptics Incorporated)
• Inventors: Shier, John S.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Romano, G.
• Application Number:
  US07/134,758
• Time in Patent Office: 585 Days
• Field of Search: 341/120, 341/121, 341/128, 341/134, 341/156, 341/159, 341/165, 341/167
• US Class Current: 341/121
• CPC Class Codes: H03M 1/1071 Measuring or testing
• CPC Class Codes: H03M 1/40 recirculation type
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 1/74 Simultaneous conversion

Abstract

A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.

Claims

1. A single chip integrated successive approximation analog-to-digital converter, including:

test mode terminal means for receiving test mode control signals and successive approximation mode control signals;

test data terminal means for receiving digital test data signals;

a trimmable digital-to-analog converter (DAC) having input terminals for receiving digital signals and for converting the digital signals to analog signals of corresponding values; and

successive approximation register means coupled to the test mode terminal means and test data terminal means for operating in a test mode and applying the test data signals to the input terminals of the DAC in response to the test mode control signals, and for operating in a successive approximation register mode in response to the successive approximation mode control signals.

2. The analog-to-digital converter of claim 1 wherein:

the test data terminal means serially receives the digital test data signals; and

the successive approximation register means comprises successive approximation and shift register means for serially receiving the test data signals and for providing the test data signals to the DAC in parallel.

3. The analog-to-digital converter of claim 2 and further including:

an input terminal for receiving analog input signals;

a comparator coupled to the input terminal and the DAC; and

a latch coupled between the comparator and the successive approximation register means.

4. The analog-to-digital converter of claim 3 wherein the successive approximation and shift register means includes bipolar transistors.

5. The analog-to-digital converter of claim 3 wherein the successive approximation and shift register means is implemented with current mode logic.