System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur
First Claim
1. A method of controlling a clock signal in an information processing system, said system includes a memory, at least one I/O device, and a clock for providing a signal to a central processor unit, said method comprising the steps of:
- selectively establishing a desired event from a plurality of events to control the supply of said clock signal to said central processor unit;
arming a control circuit which enables the supply of said clock signal to be stopped;
determining subsequent to said arming step whether said desired event has occurred;
stopping said supply of said clock signal to said central processor unit a first time in response to said arming step and said desired event has not occurred;
disarming said control unit in response to the occurrence of an interrupt generated by an I/O device or a request for memory access;
starting the supply of said clock signal to said central processor unit in response to said disarming step;
rearming said control circuit; and
stopping the supply of said clock signal to said central processor unit a second time if said interrupt or said request was not said desired event.
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Accused Products
Abstract
An apparatus and method are provided for disabling the clocking of a processor in a battery operated computer during non-processing times. The clocking is disabled at the conclusion of a processing operation. The clocking can then be re-enabled using interrupts from any one of a plurality of sources, such as an I/O device or a direct memory access. Application programs and operating system programs running on the system can specify the stopping of the system clock and the central processor until a specified event which had been requested occurs, or until an optional time-out period has expired. In this situation, the event is defined as one that results in either a system interrupt from an I/O device or from a direct memory access operation. The stopping of the system clock is a two part operation wherein in the first part the stopping mechanism is first armed. If an interrupt is received subsequent to arming, then it will be processed and the arming mechanism will be reset. However, if an interrupt does not occur after arming within a specified time period, then the system clock will be stopped.
329 Citations
10 Claims
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1. A method of controlling a clock signal in an information processing system, said system includes a memory, at least one I/O device, and a clock for providing a signal to a central processor unit, said method comprising the steps of:
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selectively establishing a desired event from a plurality of events to control the supply of said clock signal to said central processor unit; arming a control circuit which enables the supply of said clock signal to be stopped; determining subsequent to said arming step whether said desired event has occurred; stopping said supply of said clock signal to said central processor unit a first time in response to said arming step and said desired event has not occurred; disarming said control unit in response to the occurrence of an interrupt generated by an I/O device or a request for memory access; starting the supply of said clock signal to said central processor unit in response to said disarming step; rearming said control circuit; and stopping the supply of said clock signal to said central processor unit a second time if said interrupt or said request was not said desired event. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification